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PYA28C16B 반도체 회로 부품 판매점

EEPROM



PYRAMID 로고
PYRAMID
PYA28C16B 데이터시트, 핀배열, 회로
FEATURES
Access Times of 150, 200, 250 and 350ns
Single 5V±10% Power Supply
Byte Write Cycle Time - 10 ms Maximum
Low Power CMOS:
- 60 mA Active Current
- 150 µA Standby Current
Fast Write Cycle Time - DATA Polling
CMOS & TTL Compatible Inputs and Outputs
PYA28C16B
2K X 8 EEPROM
Endurance:
- 10,000 Write Cycles
- 100,000 Write Cycles (optional)
Data Retention: 10 Years
Available in the following package:
– 24-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
DESCRIPTION
The PYA28C16B is a 5 Volt 2Kx8 EEPROM. The PY-
A28C16B is a 16K memory organized as 2,048 words by
8 bits. Data Retention is 10 Years. The device is available
in a 24-Pin 600 mil wide Ceramic DIP and 32-Pin LCC.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DIP (C12)
Document # EEPROM109 REV OR
LCC (L6)
Revised October 2012


PYA28C16B 데이터시트, 핀배열, 회로
PYA28C16B - 2K x 8 EEPROM
OPERATION
READ
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE re-
turning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
BYTE WRITE
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The PYA28C16B supports both a
CE and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first. A
byte write operation, once initiated, will automatically con-
tinue to completion.
CHIP CLEAR
The contents of the entire memory of the PYA28C16B
may be set to the high state by the CHIP CLEAR opera-
tion. By setting CE low and OE to 12 volts, the chip is
cleared when a 10 msec low pulse is applied to WE.
DEVICE IDENTIFICATION
An extra 32 bytes of EEPROM memory are available to
the user for device identification. By raising A9 to 12 ±
0.5V and using address locations 7E0H to 7FFH the ad-
ditional bytes may be written to or read from in the same
manner as the regular memory array.
DATA POLLING
The PYA28C16B features DATA Polling as a method to
indicate to the host system that the byte write cycle has
completed. DATA Polling allows a simple bit test opera-
tion to determine the status of the PYA28C16B, eliminat-
ing additional interrupts or external hardware. During the
internal programming cycle, any attempt to read the last
byte written will produce the complement of that data on
I/O7 (i.e., write data=0xxx xxxx, read data=1xxx xxxx).
Once the programming cycle is complete, I/O7 will reflect
true data.
MAXIMUM RATINGS(1)
Sym Parameter
VCC
VTERM
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
6.25V)
TA Operating Temperature
TBIAS Temperature Under Bias
TSTG Storage Temperature
PT Power Dissipation
IOUT DC Output Current
Value
-0.3 to +6.25
-0.5 to +6.25
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMENDED OPERATING CONDITIONS
Grade(2)
Military
Ambient Temp GND
-55°C to +125°C 0V
VCC
5.0V ± 10%
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Sym Parameter
Conditions Typ Unit
CIN
COUT
Input Capacitance
Output Capacitance
VIN = 0V
10 pF
VOUT = 0V 10 pF
Document # EEPROM109 REV OR
Page 2




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