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PDF 5P49V5944 Data sheet ( Hoja de datos )
| Número de pieza | 5P49V5944 | |
| Descripción | Programmable Clock Generator | |
| Fabricantes | Integrated Device Technology | |
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Programmable Clock Generator
5P49V5944
DATASHEET
Description
The 5P49V5944 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The input reference can be either a crystal or an LVCMOS
reference clock.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
XOUT
XIN/REF
VDDA
GND
SD/OE
20 19 18 17 16
1 15
2 14
3
EPAD
13
4 12
5 11
6 7 8 9 10
VDDO1
OUT1
OUT1B
GND
GND
20-pin VFQFPN
Features
• Generates up to two independent output frequencies
• High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
• Two fractional output dividers (FODs)
• Independent Spread Spectrum capability on each output
pair
• Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
• I2C serial programming interface
• One reference LVCMOS output clock
• Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
• I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
• Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
– Crystal frequency range: 8MHz to 40MHz
• Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
• Programmable loop bandwidth
• Programmable output to output skew
• Programmable slew rate control
• Programmable crystal load capacitance
• Individual output enable/disable
• Power-down mode
• 1.8V, 2.5V or 3.3V core VDDD, VDDA
• Available in 20-pin VFQFPN 3mm x 3mm package
• -40° to +85°C industrial temperature operation
5P49V5944 NOVEMBER 11, 2016
1 ©2016 Integrated Device Technology, Inc.
1 page  
Reference Clock Input Pins
The 5P49V5944 supports one clock input. The clock input
(XIN/ REF) can be driven by either an external crystal or a
reference clock.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
XTAL[5:0] Tuning Capacitor Characteristics
Parameter
XTAL
Bits Step (pF) Min (pF)
6 0.5
9
Max (pF)
25
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
You can write the following equation for this capacitance:
Ci = 9pF + 0.5pF × XTAL[5:0]
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
5P49V5944 DATASHEET
You can write the following equations for the total capacitance
at each crystal pin:
CXIN = Ci1 + Cs1 + Ce1
CXOUT = Ci2 + Cs2 + Ce2
Ci1 and Ci2 are the internal, tunable capacitors. Cs1 and Cs2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
Ce1 and Ce2 are additional external capacitors that can be
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce1 and/or Ce2 to avoid
crystal startup issues. Ce1 and Ce2 can also be used to adjust
for unpredictable stray capacitance in the PCB.
The final load capacitance of the crystal:
CL = CXIN × CXOUT / (CXIN + CXOUT)
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
CXIN = CXOUT = Cx → CL = Cx / 2
The complete formula when the capacitance at both crystal
pins is the same:
CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
Example 1: The crystal load capacitance is specified as 8pF
and the stray capacitance at each crystal pin is Cs=1.5pF.
Assuming equal capacitance value at XIN and XOUT, the
equation is as follows:
8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2 →
0.5pF × XTAL[5:0] = 5.5pF → XTAL[5:0] = 11 (decimal)
Example 2: The crystal load capacitance is specified as 12pF
and the stray capacitance Cs is unknown. Footprints for
external capacitors Ce are added and a worst case Cs of 5pF
is used. For now we use Cs + Ce = 5pF and the right value for
Ce can be determined later to make 5pF together with Cs.
12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2 →
XTAL[5:0] = 20 (decimal)
NOVEMBER 11, 2016
5 PROGRAMMABLE CLOCK GENERATOR
5 Page 
5P49V5944 DATASHEET
Table 9: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down
Resistance (TA = +25 °C)
Symbol
CIN
Pull-down Resistor
ROUT
Parameter
Input Capacitance (SD/OE, SEL1/SDA, SEL0/SCL)
SD/OE, SEL1/SDA, SEL0/SCL, OUT0_SEL_I2CB
LVCMOS Output Driver Impedance (VDDO = 1.8V, 2.5V, 3.3V)
Min
100
Typ Max Unit
3 7 pF
300 kΩ
17 Ω
XIN/REF
XOUT
Programmable capacitance at XIN/REF (X1 in parallel with X2)
Programmable capacitance at XOUT (X1 in parallel with X2)
0
0
8 pF
8 pF
Table 10: Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance (CL) @ <=25 MHz
Load Capacitance (CL) >25M to 40M
Maximum Crystal Drive Level
Test Conditions
Minimum Typical Maximum
Fundamental
8 25 40
10 100
7
6 8 12
68
100
Note: Typical crystal used is FOX 603-25-150. For different reference crystal options please go to www.foxonline.com.
Units
MHz
Ω
pF
pF
pF
µW
Table 11: DC Electrical Characteristics
Symbol
Iddcore3
Parameter
Core Supply Current
Test Conditions
100 MHz on all outputs, 25 MHz
REFCLK
LVPECL, 350 MHz, 3.3V VDDOx
LVPECL, 350 MHz, 2.5V VDDOx
LVDS, 350 MHz, 3.3V VDDOx
LVDS, 350 MHz, 2.5V VDDOx
LVDS, 350 MHz, 1.8V VDDOx
HCSL, 250 MHz, 3.3V VDDOx, 2 pF load
Iddox
Output Buffer Supply Current
HCSL, 250 MHz, 2.5V VDDOx, 2 pF load
LVCMOS, 50 MHz, 3.3V, VDDOx 1,2
LVCMOS, 50 MHz, 2.5V, VDDOx 1,2
LVCMOS, 50 MHz, 1.8V, VDDOx 1,2
LVCMOS, 200 MHz, 3.3V VDDOx1
LVCMOS, 200 MHz, 2.5V VDDOx1,2
LVCMOS, 200 MHz, 1.8V VDDOx1,2
Iddpd
Power Down Current
SD asserted, I2C Programming
1. Single CMOS driver active.
2. Measured into a 5” 50 Ohm trace with 2 pF load.
3. Iddcore = IddA+ IddD, no loads.
Min
Typ
30
42
37
18
17
16
29
28
16
14
12
36
27
16
10
Max
34
47
42
21
20
19
33
33
18
16
14
42
32
19
14
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOVEMBER 11, 2016
11 PROGRAMMABLE CLOCK GENERATOR
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 5P49V5944.PDF ] | |
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