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Número de pieza MCF5249
Descripción Microprocessor
Fabricantes Freescale Semiconductor　
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No Preview Available ! MCF5249 Hoja de datos, Descripción, Manual

Freescale Semiconductor, Inc.
MCF5249
ColdFire® Integrated Microprocessor
User’s Manual
MCF5249UM/D
Rev. 4.0, 10/2003
For More Information On This Product,
Go to: www.freescale.com

1 page




MCF5249 pdf
Paragraph
Number
Freescale Semiconductor, Inc.
Table of Contents
Page
Number
3.5.7
3.5.8
3.5.9
3.5.10
3.5.11
3.5.12
3.6
3.6.1
3.6.2
3.7
3.8
3.9
3.10
Debug Interrupt .............................................................................................................3-11
RTE and Format Error Exceptions ................................................................................3-11
TRAP Instruction Exceptions ........................................................................................3-12
Interrupt Exception .......................................................................................................3-12
Fault-on-Fault Halt ........................................................................................................3-12
Reset Exception ...........................................................................................................3-12
Instruction Execution Timing ..............................................................................................3-12
Timing Assumptions .....................................................................................................3-13
MOVE Instruction Execution Times ..............................................................................3-13
Standard One Operand Instruction Execution Times ........................................................3-15
Standard Two Operand Instruction Execution Times ........................................................3-16
Miscellaneous Instruction Execution Times .......................................................................3-18
Branch Instruction Execution Times ..................................................................................3-19
4.1
4.2
4.2.1
4.2.2
4..2.3
4.3
4.4
4.5
SECTION 4
PHASE-LOCKED LOOP AND CLOCK DIVIDERS
PLL Features .......................................................................................................................4-1
PLL Programming ................................................................................................................4-2
PLL Operation ................................................................................................................4-4
PLL Lock-in Time ............................................................................................................4-4
PLL Electrical Limits .......................................................................................................4-4
Audio Clock Generation .......................................................................................................4-5
Reduced Power Mode .........................................................................................................4-6
Recommended Settings ......................................................................................................4-6
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.4
5.4.1
5.4.2
5.4.2.1
5.4.2.2
SECTION 5
INSTRUCTION CACHE
Instruction Cache Features ..................................................................................................5-1
Instruction Cache Physical Organization .............................................................................5-1
Instruction Cache Operation ................................................................................................5-2
Interaction with Other Modules .......................................................................................5-2
Memory Reference Attributes .........................................................................................5-3
Cache Coherency and Invalidation .................................................................................5-3
Reset ..............................................................................................................................5-3
Cache Miss Fetch Algorithm/Line Fills ............................................................................5-3
Instruction Cache Programming Model ...............................................................................5-5
Instruction Cache Registers Memory Map ......................................................................5-5
Instruction Cache Register .............................................................................................5-6
Cache Control Register .............................................................................................5-6
Access Control Registers ..........................................................................................5-8
MOTOROLA
Table of Contents
For More Information On This Product,
Go to: www.freescale.com
TOC-3

5 Page





MCF5249 arduino
Paragraph
Number
Freescale Semiconductor, Inc.
Table of Contents
Page
Number
15.4.1.3
15.4.1.4
15.4.1.5
15.4.1.6
15.4.1.6.1
15.4.1.6.2
15.4.1.6.3
15.4.1.6.4
15.4.1.6.5
15.4.1.6.6
15.4.1.6.7
15.4.1.7
15.4.1.7.1
15.4.1.7.2
15.4.1.7.3
15.4.1.7.4
15.4.1.8
15.4.1.8.1
15.4.1.8.2
15.4.1.8.3
15.4.1.8.4
15.4.1.9
15.4.1.10
15.4.1.11
15.4.1.12
15.4.1.13
15.4.1.14
15.4.1.15
15.4.1.16
15.4.1.17
15.4.1.18
15.4.1.19
15.4.2
15.4.2.1
15.4.2.2
15.4.1.3
15.5
Status Registers (USRn) .......................................................................................15-18
Clock-Select Registers (USCRn) ...........................................................................15-19
Command Registers (UCRn) .................................................................................15-20
Miscellaneous Commands ....................................................................................15-20
Reset Mode Register Pointer ...........................................................................15-21
Reset Receiver .................................................................................................15-21
Reset Transmitter .............................................................................................15-21
Reset Error Status ............................................................................................15-21
Reset Break-Change Interrupt .........................................................................15-21
Start Break .......................................................................................................15-21
Stop Break ........................................................................................................15-21
Transmitter Commands .........................................................................................15-21
No Action Taken ...............................................................................................15-22
Transmitter Enable ...........................................................................................15-22
Transmitter Disable ..........................................................................................15-22
Do Not Use .......................................................................................................15-22
Receiver Commands .............................................................................................15-22
No Action Taken ...............................................................................................15-22
Receiver Enable ...............................................................................................15-22
Receiver Disable ..............................................................................................15-23
Do Not Use .......................................................................................................15-23
Receiver Buffer Registers (UBRn) .........................................................................15-23
Transmitter Buffer Registers (UTBn) .....................................................................15-23
Input Port Change Registers UIPCRn) ..................................................................15-24
Auxiliary Control Registers (UACRn) .....................................................................15-24
Interrupt Status Registers (UISRn) ........................................................................15-25
Interrupt Mask Registers UIMRn) ..........................................................................15-26
Timer Upper Preload Register (UBG1n) ................................................................15-27
Timer Upper Preload Register 2 (UBG2n) .............................................................15-27
Interrupt Vector Registers (UIVRn) ........................................................................15-27
Input Port Registers (UIPn) ...................................................................................15-28
Output Port Data Registers (UOP1n) ....................................................................15-28
Programming ..............................................................................................................15-29
UART Module Initialization ....................................................................................15-29
I/O Driver Example ................................................................................................15-29
Interrupt Handling ..................................................................................................15-29
UART Module Initialization Sequence .............................................................................15-30
16.1
16.2
16.3
16.3.1
16.3.2
16.4
16.4.1
16.4.1.1
16.4.1.2
16.4.1.3
16.4.2
SECTION 16
QUEUED SERIAL PERIPHERAL INTERFACE (QSPI) MODULE
Overview ............................................................................................................................16-1
Features .............................................................................................................................16-1
Module Description ............................................................................................................16-1
Interface and Pins .........................................................................................................16-1
Internal Bus Interface ...................................................................................................16-2
Operation ...........................................................................................................................16-3
QSPI RAM ....................................................................................................................16-3
Transmit RAM ..........................................................................................................16-5
Receive RAM ...........................................................................................................16-5
Command RAM .......................................................................................................16-5
Baud Rate Selection .....................................................................................................16-6
MOTOROLA
Table of Contents
For More Information On This Product,
Go to: www.freescale.com
TOC-9

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