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PDF X9015 Data sheet ( Hoja de datos )

Número de pieza X9015
Descripción Single Digitally Controlled Potentiometer
Fabricantes Intersil 
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®
Data Sheet
X9015
Low Noise, Low Power, Volatile
August 31, 2006
FN8157.5
Single Digitally Controlled (XDCP™)
Potentiometer
The Intersil X9015 is a 32 tap potentiometer that is volatile.
The device consists of a string of 31 resistors that can be
programmed to connect the RW/VW wiper output with any of
the nodes between the connecting resistors. The connection
point of the wiper is determined by information
communicated to the device on the 3-wire port. The 3-wire
port changes the tap position by a falling edge on the
increment pin. The direction the wiper moves is determined by
the state of the up/down pin. The wiper position at power up is
Tap #15.
The X9015 can be used in a wide variety of applications that
require a digitally controlled variable resistor to set analog
values.
Features
• 32 taps
• Three-wire up/down serial interface
• VCC = 2.7V–5V
• Operating ICC = 50µA max.
• Standby current = 1µA max.
• RTOTAL = 10kΩ, 50kΩ
• Packages 8 Ld SOIC, 8 Ld MSOP
• Pb-free plus anneal available (RoHS compliant)
Pinout
SOIC/MSOP
INC
U/D
RH/VH
VSS
1
2
X9015
3
4
8
7
6
5
VCC
CS
RL/VL
RW/VW
Block Diagram
www.DataSheet4U.com
VCC (Supply Voltage)
Up/Down
(U/D)
Increment
(INC)
Device Select
(CS)
Control
VSS (Ground)
General
U/D
INC
CS
RH/VH
RW/VW
RL/VL
VCC
VSS
5-Bit
Up/Down
Counter
Control
Circuitry
31
30
29
One 28
of
Thirty
Two
Decoder
2
1
0
Transfer
Gates
Resistor
Array
Detailed
RH/VH
RL/VL
RW/VW
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




X9015 pdf
X9015
)
D.C. Operating Specifications Over recommended operating conditions unless otherwise specified
SYMBOL
ICC1
PARAMETER
VCC active current (increment)
ICC2
ISB
VCC active current (Store) (EEPROM
Store)
Standby supply current
ILI CS, INC, U/D input leakage current
VIH CS, INC, U/D input HIGH voltage
VIL CS, INC, U/D input LOW voltage
CIN (Note 5) CS, INC, U/D input capacitance
TEST CONDITIONS
CS = VIL, U/D = VIL or VIH and
INC = 0.4V @ max. tCYC
CS = VIH, U/D = VIL or VIH and
INC = VIH @ max. tWR
CS = VCC – 0.3V, U/D and
INC = VSS or VCC – 0.3V
VIN = VSS to VCC
VCC = 5V, VIN = VSS, TA = 25°C,
f = 1MHz
MIN.
VCC x 0.7
-0.5
TYP.
(Note 4)
MAX.
50
400
1
±10
VCC + 0.5
VCC x 0.1
10
UNITS
µA
µA
µA
µA
V
V
pF
TEST CIRCUIT #1
TEST CIRCUIT #2
VH/RH
VS Test Point
VW/RW
VL/RL
VH/RH
Test Point
VWW/RW
Force
VVLL/RL
Current
Symbol Table
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
A.C. Conditions of Test
Input pulse levels
Input rise and fall times
Input reference levels
0V to 3V
10ns
1.5V
CIRCUIT #3 SPICE MACRO MODEL
RTOTAL
RH RL
CH
CW CL
10pF
10pF
25pF
RW
5 FN8157.5
August 31, 2006

5 Page





X9015 arduino
X9015
Mini Small Outline Plastic Packages (MSOP)
N
E1 E
INDEX
AREA
A A2
12
TOP VIEW
-B-
0.20 (0.008) A B C
GAUGE
PLANE
0.25
(0.010)
4X θ
R1
R
SEATING
PLANE -C-
L
4X θ
L1
A1 -H-
b
e
D
SEATING
0.10 (0.004) C PLANE
-A-
0.20 (0.008) C
C
SIDE VIEW
a
0.20 (0.008) C D
CL
E1 -B-
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A - and - B - to be determined at Datum plane
-H- .
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.037 0.043 0.94
1.10
-
A1
0.002 0.006 0.05
0.15
-
A2
0.030 0.037 0.75
0.95
-
b
0.010 0.014 0.25
0.36
9
c
0.004 0.008 0.09
0.20
-
D
0.116 0.120 2.95
3.05
3
E1
0.116 0.120 2.95
3.05
4
e 0.026 BSC
0.65 BSC
-
E
0.187 0.199 4.75
5.05
-
L
0.016 0.028 0.40
0.70
6
L1 0.037 REF
0.95 REF
-
N8
87
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
0 5o 15o 5o 15o
α 0o 6o 0o 6o
-
-
-
Rev. 2 01/03
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN8157.5
August 31, 2006

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