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PDF F50L1G41A Data sheet ( Hoja de datos )
| Número de pieza | F50L1G41A | |
| Descripción | 3.3V 1 Gbit SPI-NAND Flash Memory | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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ESMT
Flash
PRODUCT LIST
Parameters
VCC
Width
Frequency
Internal ECC Correction
Transfer Rate
Loading Throughput
Power-up Ready Time
Max Reset Busy Time
Note: 1. x2 PROGRAM operation is not defined.
F50L1G41A (2Y)
3.3V 1 Gbit
SPI-NAND Flash Memory
Values
3.3V
x1, x21, x4
104MHz
1-bit
9.6ns
104MT/s
1ms (maximum value)
1ms (maximum value)
FEATURES
z Voltage Supply: 3.3V (2.7V~3.6V)
z Organization
- Memory Cell Array: (128M + 4M) x 8bit
- Data Register: (2K + 64) x 8bit
z Automatic Program and Erase
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
z Page Read Operation
- Page Size: (2K + 64) Byte
- Read from Cell to Register with Internal ECC: 100us
z Memory Cell: 1bit/Memory Cell
z Support SPI-Mode 0 and SPI-Mode 31
z Fast Write Cycle Time
- Program time:400us
- Block Erase time: 4ms
z Hardware Data Protection
- Program/Erase Lockout During Power Transitions
z Reliable CMOS Floating Gate Technology
- Internal ECC Requirement: 1bit/512Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
z Command Register Operation
z NOP: 4 cycles
z OTP Operation
z Bad-Block-Protect
z Boot Read
Note: 1. Mode 0: CPOL = 0, CPHA = 0; Mode 3: CPOL = 1, CPHA = 1
ORDERING INFORMATION
Product ID
F50L1G41A -104RAG2Y
Speed
104MHz
Package
8-contact LGA 8x6mm
Comments
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
1/36
1 page  
ESMT
F50L1G41A (2Y)
COMMAND SET
Function
Op Code Address Byte
Dummy Byte
Data Bytes
BLOCK ERASE
1
GET FEATURE
SET FEATURE
WRITE DISABLE
WRITE ENABLE
PROGRAM LOAD
2
PROGRAM LOAD x4
PROGRAM LOAD RANDOM
DATA
PROGRAM LOAD RANDOM
2
DATA x4
PROGRAM EXECUTE
PAGE READ
READ FROM CACHE
READ FROM CACHE x2
2
READ FROM CACHE x4
3
READ ID
RESET
D8h
0Fh
1Fh
04h
06h
02h
32h
84h
34h
10h
13h
03h, 0Bh
3Bh
6Bh
9Fh
FFh
3
1
1
0
0
2
2
2
2
3
3
2
2
2
1
0
00
01
01
00
00
0 1 to 2112
0 1 to 2112
0 1 to 2112
0 1 to 2112
00
00
1 1 to 2112
1 1 to 2112
1 1 to 2112
02
00
Note:
1. Refer to Feature Register.
2. Command/Address is 1-bit input per clock period, data is 4-bit input/output per clock period.
3. Address is 00h to get JEDEC ID
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
5/36
5 Page 
ESMT
GET FEATURE (0Fh) Timing
F50L1G41A (2Y)
SET FEATURE (1Fh) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
11/36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet F50L1G41A.PDF ] | |
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