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Elite Semiconductor |
ESMT
Flash
F25L16PA (2S)
16 Mbit Serial Flash Memory
with Dual
FEATURES
y Single supply voltage 2.7~3.6V
y Standard and Dual
y Speed
- Read max frequency: 50MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz / 100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI)
y Low power consumption
- Active current: 23.5 mA (max.)
- Standby current: 25 μ A (max.)
- Deep Power Down current: 10 μ A (max.)
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Page programming time: 1.5 ms (typical)
y Erase
- Chip Erase time 10 sec (typical)
- 64K bytes Block Erase time 1 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 120 ms (typical)
y Page Programming
- 256 byte per programmable page
y Lockable 512 bytes OTP security sector
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
Speed
F25L16PA –50PG2S
50MHz
F25L16PA –86PG2S
86MHz
F25L16PA –100PG2S 100MHz
F25L16PA –50PAG2S 50MHz
F25L16PA –86PAG2S 86MHz
F25L16PA –100PAG2S 100MHz
F25L16PA –50PHG2S 50MHz
F25L16PA –86PHG2S 86MHz
F25L16PA –100PHG2S 100MHz
F25L16PA –50DG2S
50MHz
F25L16PA –86DG2S
86MHz
F25L16PA –100DG2S 100MHz
F25L16PA –50HG2S
50MHz
F25L16PA –86HG2S
86MHz
F25L16PA –100HG2S 100MHz
Package
Comments
8-lead
SOIC
150 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
16-lead
SOIC
300 mil
Pb-free
8-pin
PDIP
300 mil
Pb-free
8-contact
WSON
6x5 mm
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
1/42
ESMT
F25L16PA (2S)
GENERAL DESCRIPTION
The F25L16PA is a 16Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 8,192 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
is divided into 512 uniform sectors with 4K byte each; 64 uniform
blocks with 32K byte each; 32 uniform blocks with 64K byte each.
Sectors can be erased individually without affecting the data in
other sectors. Blocks can be erased individually without affecting
the data in other blocks. Whole chip erase capabilities provide
the flexibility to revise the data in the device. The device has
Sector, Block or Chip Erase but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
FUNCTIONAL BLOCK DIAGRAM
Page Address
Latch / Counter
High Voltage
Generator
Status
Register
Byte Address
Latch / Counter
Memory
Array
Page Buffer
Y-Decoder
Command and Conrol Logic
Serial Interface
CE SCK
SI
SO WP HOLD
(SIO0) (SIO1)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
2/42
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