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PDF LE24L042CS-B Data sheet ( Hoja de datos )
| Número de pieza | LE24L042CS-B | |
| Descripción | Two Wire Serial Interface EEPROM | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA2068
LE24L042CS-B
CMOS IC
Two Wire Serial Interface EEPROM
(4k EEPROM)
http://onsemi.com
Overview
The LE24L042CS-B is a 2-wire serial interface EEPROM. It realizes high speed and a high level reliability by
incorporating high performance CMOS EEPROM technology. This device is compatible with I2C memory protocol,
therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory.
Functions
• Capacity: 4k bits (512 × 8 bits)
• Single supply voltage: 1.7V to 3.6V
• Interface: Two wire serial interface (I2C Bus*)
• Operating clock frequency: 400kHz
• Low power consumption
: Standby: 2μA (max)
: Active (Read): 0.5mA (max)
• Automatic page write mode: 16 Bytes
• Read mode: Sequential read and random read
• Erase/Write cycles: 105 cycles
• Data Retention: 20 years
• High reliability: Adopts proprietary symmetric memory array configuration (USP6947325)
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
* I2C Bus is a trademark of Philips Corporation.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
July, 2013
60612 SY 20101116-S00006 No.A2068-1/11
1 page  
LE24L042CS-B
Functional Description
1 Start condition
When the SCL line is at the high level, the start condition is established by changing the SDA line from high to low.
The operation of the EEPROM as a slave starts in the start condition.
2 Stop condition
When the SCL line is at the high level, the stop condition is established by changing the SDA line from low to high.
When the device is set up for the read sequence, the read operation is suspended when the stop condition is received,
and the device is set to standby mode. When it is set up for the write sequence, the capture of the write data is ended
when the stop condition is received, and the EEPROM internal write operation is started.
SCL
SDA
tSU.STA tHD.STA
Start
condition
tSU.STO
Stop
condition
3 Data transfer
Data is transferred by changing the SDA line while the SCL line is low. When the SDA line is changed while the SCL
line is high, the resulting condition will be recognized as the start or stop condition.
SCL
SDA
tSU.DAT
tHD.DAT
4 Acknowledge
During data transfer, 8 bits are transferred in succession, and then in the ninth clock cycle period the device on the
system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has
been received. The acknowledge signal is not sent during an EEPROM internal write operation.
SCL
(EEPROM input)
SDA
(Master output)
SDA
(EEPROM output)
Start
condition
1
89
Acknowledge
bit output
tAA
tDH
No.A2068-5/11
5 Page 
LE24L042CS-B
6) Slave address settings
This product does not come with any slave address pins, but the information of the S0, S1 and S2 slave addresses is
held internally. S1 = 0 and S2 = 0 were set for the slave addresses before shipment. During device addressing, these
slave address codes must be executed following the device code.
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PS No.A2068-11/11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet LE24L042CS-B.PDF ] | |
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