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Semtech |
PROTECTION PRODUCTS - RailClamp®
Description
The RClamp®3328P provides low voltage ESD protec-
tion for high-speed ports. It features a high maximum
ESD withstand voltage of ±25kV contact and ±30kV
air discharge per IEC 61000-4-2. RClamp3328P is
designed to minimize both the ESD peak clamping and
the TLP clamping. Peak ESD clamping voltage is
extremely low and approximately the same at each pin.
The dynamic resistance is among the industry’s lowest
at 0.35 Ohms (typical). Maximum capacitance on each
line to ground is 0.65pF. This allows the
RClamp3328P to be used in applications operating in
excess of 5GHz without signal attenuation. These
devices are manufactured using Semtech’s proprietary
low voltage EPD technology for superior characteritics
at operating voltages up to 3.3 volts. Each device will
protect up to eight lines (four high-speed pairs).
The RClamp3328P is in a 9-pin SGP3810N9 package. It
measures 3.8 x 1.0mm with a nominal height of 0.50mm.
Intra-pair lead pitch is 0.40mm while the pair-to-pair pitch
is 0.5mm. The innovative flow through package design
simplifies pcb layout and allows matched trace lengths
for consistant impedance between high speed differen-
tial lines.
The combination of low peak ESD clamping, low dynamic
resistance, and innovative package design enables this
device provides the highest level of ESD protection for
applications such as USB 3.0, HDMI and V-By-One inter-
faces.
Dimensions
RClamp3328P
Low Capacitance RClamp®
8-Line ESD Protection
PRELIMINARY
Features
ESD protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±30kV (air), ±25kV (contact)
IEC 61000-4-5 (Lightning) 5A (8/20μs)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Package design optimized for high speed lines
Flow-Through design
Protects eight high-speed lines
Low capacitance: 0.65pF Maximum (I/O to Ground)
Low ESD clamping voltage
Low dynamic resistance: 0.35 Ohms (Typ)
Solid-state silicon-avalanche technology
Mechanical Characteristics
SGP3810N9 9-pin package (3.8 x 1.0 x 0.50mm)
Pb-Free, Halogen Free, RoHS/WEEE Compliant
Lead Pitch: 0.4mm (intra-pair), 0.50mm (pair-to-
pair)
Lead finish: NiPdAu
Marking: Marking Code
Packaging: Tape and Reel
Applications
HDMI 1.3/1.4
V-By-One
USB 3.0
eDP
MHL
LVDS Interfaces
eSATA Interfaces
Circuit Diagram
3.80
0.40 BSC
0.50 BSC
1.00
0.50
Nominal Dimensions in mm (Bottom View)
Revision 7/18/2013
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8-Line Protection
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PROTECTION PRODUCTS
Absolute Maximum Rating
Rating
Peak Pulse Power (tp = 8/20μs)
Peak Pulse Current (tp = 8/20μs)
ESD per IEC 61000-4-2 (Air)1
ESD per IEC 61000-4-2 (Contact)1
Operating Temperature
Storage Temperature
Electrical Characteristics (T=25oC)
Symbol
Ppk
IPP
VESD
TJ
TSTG
RClamp3328P
PRELIMINARY
Value
75
5
+/- 30
+/- 25
-55 to +125
-55 to +150
Units
Watts
A
kV
°C
°C
Parameter
Symbol
Conditions
Minimum Typical Maximum Units
Reverse Stand-Off Voltage
Punch-Through Voltage
VRWM
VPT
Any I/O to GND
IPT = 2μA
Any I/O to GND
3.3 V
3.8 4.8 5.5 V
Reverse Leakage Current
IR VRWM = 3.3V,
Any I/O to GND
0.005
0.100
μA
Clamping Voltage
VC IPP = 1A, tp = 8/20μs
Any I/O to GND
5.2 7 V
Clamping Voltage
VC IPP = 5A, tp = 8/20μs
Any I/O to GND
8.2 10.5 V
ESD Clamping Voltage2
VC IPP = 16A,
tlp = 0.2/100ns
11.8
V
ESD Clamping Voltage2
VC
IPP = -16A,
tlp = 0.2/100ns
11.7
V
Dynamic Resistance (Positive)2,3
Dynamic Resistance(negative)2,3
Junction Capacitance
RD
RD
Cj
tp = 100ns
tp = 100ns
VR = 0V, f = 1MHz,
Any I/O to GND
0.35
0.50
0.40
0.65
Ohms
Ohms
pF
VBRe=tw0eVe,nf
= 1MHz,
I/O pins
0.30 0.4 pF
Notes
1)Measured with a 20dB attenuator, 50 Ohm scope input impedance, 2GHz bandwidth. ESD gun return path
connected to ESD ground plane.
2)Transmission Line Pulse Test (TLP) Settings: tp = 100ns, tr = 0.2ns, ITLP and VTLP averaging window: t1 = 70ns to
t2 = 90ns.
3) Dynamic resistance calculated from ITLP = 4A to ITLP = 16A
© 2013 Semtech Corporation
2
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