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NP110N055PUJ 반도체 회로 부품 판매점

N-CHANNEL POWER MOS FET



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NP110N055PUJ 데이터시트, 핀배열, 회로
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP110N055PUJ
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The NP110N055PUJ is N-channel MOS Field Effect Transistor designed for high current switching applications.
ORDERING INFORMATION
PART NUMBER
NP110N055PUJ-E1B-AY Note
NP110N055PUJ-E2B-AY Note
LEAD PLATING
Pure Sn (Tin)
PACKING
Tape 1000 p/reel
Note Pb-free (This product does not contain Pb in external electrode.)
PACKAGE
TO-263 (MP-25ZP) typ. 1.5 g
FEATURES
Super low on-state resistance
RDS(on) = 2.4 mΩ MAX. (VGS = 10 V, ID = 55 A)
Low input capacitance
Ciss = 9500 pF TYP.
Designed for automotive application and AEC-Q101 qualified
(TO-263)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
55
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
ID(DC)
ID(pulse)
±110
±440
Total Power Dissipation (TC = 25°C)
PT1
288
Total Power Dissipation (TA = 25°C)
PT2
1.8
Channel Temperature
Tch 175
Storage Temperature
Single Avalanche Energy Note2
Repetitive Avalanche Current Note3
Repetitive Avalanche Energy Note3
Tstg 55 to +175
EAS 435
IAR 66
EAR 435
V
V
A
A
W
W
°C
°C
mJ
A
mJ
Notes 1. PW 10 μs, Duty Cycle 1%
2. Starting Tch = 25°C, VDD = 28 V, RG = 25 Ω, VGS = 20 0 V, L = 100 μH
3. Tch 150°C, RG = 25 Ω
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
0.52
83.3
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D19731EJ1V0DS00 (1st edition)
Date Published April 2009 NS
Printed in Japan
2009


NP110N055PUJ 데이터시트, 핀배열, 회로
NP110N055PUJ
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = 55 V, VGS = 0 V
Gate Leakage Current
IGSS VGS = ±20 V, VDS = 0 V
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(th)
| yfs |
RDS(on)
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 55 A
VGS = 10 V, ID = 55 A
Input Capacitance
Ciss VDS = 25 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 28 V, ID = 55 A,
Rise Time
tr VGS = 10 V,
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG VDD = 44 V,
Gate to Source Charge
QGS VGS = 10 V,
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
ID = 110 A
IF = 110 A, VGS = 0 V
Reverse Recovery Time
trr IF = 110 A, VGS = 0 V,
Reverse Recovery Charge
Note Pulsed test
Qrr di/dt = 100 A/μs
MIN. TYP. MAX. UNIT
1 μA
±100 nA
2.0 3.0 4.0
V
55 117
S
1.9 2.4 mΩ
9500 14250 pF
1060 1590 pF
320 580 pF
45 100 ns
20 50 ns
100 200 ns
10 30 ns
150 230 nC
35 nC
45 nC
0.9 1.5
V
64 ns
138 nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off) tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet D19731EJ1V0DS




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