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PDF 64F2646 Data sheet ( Hoja de datos )
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Hitachi 16-Bit Single-Chip Microcomputer
H8S/2646 Series
H8S/2646
HD6432646
H8S/2645
HD6432645
H8S/2647
HD6432647
H8S/2648
HD6432648
H8S/2646R F-ZTAT™
HD64F2646R
H8S/2648R F-ZTAT™
HD64F2648R
Hardware Manual
ADE-602-207C
Rev. 4.0
9/20/02
Hitachi, Ltd.
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
1 page  
Preface
The H8S/2646 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600
CPU core, and a set of on-chip supporting functions required for system configuration.
This LSI is equipped with a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG),
watchdog timer (WDT), serial communication interface (SCI), A/D converter, motor control
PWM timer (PWM), LCD controller/driver (LCDC) and I/O ports as on-chip supporting modules.
In addition, data transfer controller (DTC) is provided, enabling high-speed data transfer without
CPU intervention. This LSI is suitable for use as an embedded processor for high-level control
systems. Its on-chip ROM are flash memory (F-ZTAT™*) that provides flexibility as it can be
reprogrammed in no time to cope with all situations from the early stages of mass production to
full-scale mass production. This is particularly applicable to application devices with
specifications that will most probably change.
Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using the H8S/2646 Series in the
design of application systems. Members of this audience are expected to understand
the fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2646 Series to the above audience. Refer to the
H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description
of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
• In order to understand the details of a register when its name is known
The addresses, bits, and initial values of the registers are summarized in Appendix B, Internal
I/O Registers.
Example: Bit order: The MSB is on the left and the LSB is on the right.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.hitachisemiconductor.com/
5 Page 
Section
15.3.7 Interrupt
Interface
Table 15-5 HCAN
Interrupt Sources
Page Description
583 IRR3
IRR4
IRR7
Error warning interrupt (TEC ≥ 96)
Error warning interrupt (REC ≥ 96)
Overload frame transmission interrupt
15.5 Usage Notes 587
9. HTxD pin output
in error passive state
10. Transition to
HCAN sleep mode
11. Message
transmission
cancellation (TxCR)
12. TxCR in the bus
off state
18.1.4 Register
Configuration
Table 18-2 LCD
Controller/Driver
Registers
22.6.3 Setting
Oscillation
Stabilization Time
after Clearing
Software Standby
Mode
633
743
Newly added
9. HTxD pin output in error passive state
If the HRxD pin becomes fixed at 1 during message transmission or
reception when the HCAN is in the error active state, the HTxD pin will
output 0 continuously while in the error passive state. To stop continuous 0
output to the CAN bus, disable the HCAN by means of an error warning
interrupt or by setting the HCAN module stop mode through detection of a
fixed 1 state by the HxRD pin monitor.
10. Transition to HCAN sleep mode
The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0
immediately after an HCAN sleep mode transition effected by setting TXPR
of the HCAN to 1 and setting MCR5 to 1. When a transition is made to the
HCAN sleep mode by means of the above steps, a 10-cycle wait should be
inserted after the TxPR setting. After an HCAN sleep mode transition,
release the HCAN sleep mode by clearing MCR5 to 0.
11. Message transmission cancellation (TxCR)
If all the following conditions are met when cancellation of a transmission
message is performed by means of TxCR of the HCAN, the TxCR or TxPR
bit indicating cancellation is not cleared even though internal transmission
is canceled.
When canceling a message using TxCR, 1 should be written continuously
until TxCR or TxPR becomes 0.
12. TxCR in the bus off state
If TxPR is set before the HCAN goes to the bus off state, and a transition is
made to the bus off state with transmission incomplete, cancellation will be
performed even if TxCR is set during the bus off period, and the message
will be transmitted after a transition to the error active state.
LCD RAM
Module stop control
register D
—
MSTPCRD
Note * 2 deleted
Note amended
Note: * Do not use this setting.
R/W
R/W
Undefined
B'11******
H'FC40 to H'FC53
H'FC60
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