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PDF IS1690S Data sheet ( Hoja de datos )
| Número de pieza | IS1690S | |
| Descripción | Bluetooth 3.0 Multi-Speaker Stereo Audio SOC | |
| Fabricantes | ISSC | |
| Logotipo |  |
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IS1690S SoC
Bluetooth® 3.0 Multi-Speaker Stereo Audio SOC
Features
System Specification
Compliant with Bluetooth Specification v.3.0 +
EDR in 2.4 GHz ISM band
It supports following profiles :
- Hands Free 1.5
- Headset 1.0
- A2DP 1.0
- AVRCP 1.0
Baseband Hardware
16MHz main clock input
Built-in internal ROM for program memory
Support to connect to two hosts ( phones,
tablets…) with HFP or A2DP profiles
simultaneously
Adaptive Frequency Hopping (AFH) avoids
occupied RF channels
Fast Connection supported
RF Hardware
Fully Bluetooth 3.0 + EDR system in 2.4 GHz
ISM band.
Combined TX/RX RF terminal simplifies external
matching and reduces external antenna
switches.
Max. +4dBm output power with 20 dB level
control from register control.
Built-in T/R switch for Class 2/3 application
To avoid temperature variation, temperature
sensor with temperature calibration is utilized
into bias current and gain control.
Fully integrated synthesizer has been created.
There requires no external VCO, varactor diode,
resonator and loop filter.
Crystal oscillation with built-in digital trimming for
temperature/process variations.
Audio processor
Support A-Law or -Law PCM format, or CVSD
(Continuous Variable Slope Delta Modulation)
for SCO channel operation.
Noise suppression
Echo suppression
SBC decoding
Packet loss concealment
Build-in one languages (English) voice prompts
and 20 events for each one
Support SCMS-T
Audio Codec
16 bit DAC and 16 bit ADC codec
94dB SNR DAC playback
85 dB SNR ADC.
Peripherals
Built-in Lithium-ion battery charger (up to 350mA)
Integrate 3V, 1.8V configurable switching regulator
and LDO
Built-in ADC for battery monitor and voltage sense.
A aux-in port for external audio input
Two LED drivers
Flexible HCI interface
High speed HCI-UART (Universal Asynchronous
Receiver Transmitter) interface (up to 921600bps)
Package
7x7mm2 56QFN package
Description
IS1690S multi-speaker stereo audio chip is a
compact, highly integrated, CMOS single-chip RF and
baseband IC for Bluetooth v3.0 with Enhanced Data
Rate 2.4GHz applications. This chip is fully compliant
with Bluetooth specification and completely backward-
compatible with Bluetooth 2.0 or 1.2 systems.
It incorporates Bluetooth 1M/2M/3Mbps RF, single-
cycle 8bit MCU, TX/RX modem, 5-port memory
controller, task/hopping controller, UART interface,
and ISSC’s own Bluetooth software stack to achieve
the required BT v3.0 with EDR functions.
To provide the superior audio and voice quality, it
also integrates a DSP co-processor, a PLL, and a
CODEC dedicated for voice and audio applications.
For voice, not only basic CVSD encoding and
decoding but also enhanced noise reduction and echo
cancellation are implemented by the built-in DSP to
achieve better quality in both sending and receiving
sides. For the enhanced audio applications, SBC
decoding functions can be also carried out by DSP to
satisfy Bluetooth A2DP requirements.
page 1
1 page  
2.0 KEY FEATURES TABLE
SPEC
Chip
Application
Stereo/Mono
Pin count
Dimension (mm2)
Audio DAC output
DAC (cap-less) [email protected] (dB)
ADC SNR @2.8V (dB)
I2S digital interface
Analog aux-in
Mono MIC
Support external audio amplifier
Built-in class-D audio amplifier
UART
LED Driver
Internal DC-DC step-down regulator
DC 5V ADAPTER
Battery charger (350mA max)
IO for application
Switches support
Support NFC application
Voice prompt
Multi-tone
DSP sound effects
Built-in EEPROM
Profile
A2DP
AVRCP
HFP
HSP
PBAP
SPP
Support the feature
IS1690S
Multi-SPK
Stereo
56
7X7
2-ch
-94
-85
X
1
X
X
2
10
6
X
1.0
1.0
1.5
1.0
X
X
IS1690S SoC
page 5
5 Page 
IS1690S SoC
5.0 MICROPROCESSOR
A single-cycle 8-bit MCU is built into IS1690S multi-speaker chip to execute the Bluetooth protocols. It operates from
16MHz to 48MHz where the firmware can dynamically adjust the tradeoff between the computing power and the power
consumption. The MCU firmware is hard-wired in ROM to minimize the firmware execution power consumption and to
save the external flash cost.
5.1 MEMORY
A synchronous single port RAM interface is used. There are sufficient ROM (336KB) and RAM (36KB) to fulfill the
requirement of processor. A register bank, a dedicated single port memory and a flash memory are connected to the
processor bus. The processor coordinates all the link control procedures and data movement using a set of pointers
registers.
5.2 EXTERNAL RESET
The chip provides a watchdog timer to reset the chip. It has an integrated Power-On Reset (POR) circuit that resets
all circuits to a known power-on state. This action can also be driven by an external reset signal that can be used to
externally control the device, forcing it into a power-on reset state. The RST signal input is active low and no connection
is required in most applications.
5.3 REFERENCE CLOCK
IS1690S chip is composed of an integrated crystal oscillation function. It uses a 16 MHz external crystal and two
specified loading capacitors to provide a high quality system reference timer source. This feature is typically used to
remove the initial tolerance frequency errors associated with the crystal and its equivalent loading capacitance in mass
production. Frequency trim is achieved by adjusting the crystal loading capacitance through the on-chip trim capacitors
CTRIM..
The value of trimming capacitance is around 200fF (200x10-15 F) per LSB at 5 bits word, therefore the overall
adjustable clock frequency is around 40 KHz.
IS1690
XO_P
XO_N
CC
L1 L2
CTRIM= 200fF*(1~31)
CL=[(CL1*CL2)/(CL1+CL2)]+CTRIM
* For CL selection, please refer to the datasheet of crystal vendor
page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS1690S.PDF ] | |
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