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Número de pieza | A3S56D30GTP | |
Descripción | 256M Double Data Rate Synchronous DRAM | |
Fabricantes | Zentel | |
Logotipo | ||
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No Preview Available ! A3S56D30GTP
A3S56D40GTP
256M Double Data Rate Synchronous DRAM
256Mb DDR SDRAM Specification
A3S56D30GTP
A3S56D40GTP
Zentel Electronics Corp.
Revision 1.1
Jul., 2013
1 page Block Diagram
A3S56D30GTP
DLL
A3S56D30GTP
A3S56D40GTP
256M Double Data Rate Synchronous DRAM
DQ0 - 7
DQS
I/O Buffer
DQS Buffer
Memory
Array
Bank #0
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
A0-12 BA0,1
Clock Buffer
Control Signal Buffer
/CS /RAS /CAS /WE DM
CLK /CLK CKE
Type Designation Code
A 3 S 56 D 3 0G TP - 50
This rule is applied to only Synchronous DRAM family.
Speed
50: 200MHz@CL=3, 166MHz@CL=2.5, and 133MHz@CL=2
Package Type
TP: TSOP II
Die Version
0G: Version 0G
I/O Configuration 3: x 8
Classification
D: DDR Synchronous DRAM
Density
56: 256Mb
Interface
S: SSTL_2
Product Line
3: DRAM
Zentel Memory
Revision 1.1
Page 4 / 40
Jul., 2013
5 Page A3S56D30GTP
A3S56D40GTP
256M Double Data Rate Synchronous DRAM
Function Truth Table (continued)
Current State /CS /RAS /CAS /WE Address
WRITE H X X X X
(Auto L H H H X
Precharge L H H L BA
Disabled)
L H L H BA, CA, A10
L H L L BA, CA, A10
Command
Action
DESEL
NOP (Continue Burst to END)
NOP NOP (Continue Burst to END)
TERM
ILLEGAL
READ / READA
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge
WRITE / WRITEA
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge
Notes
3
3
L L H H BA, RA
ACT
Bank Active / ILLEGAL
2
L L H L BA, A10 PRE / PREA
Terminate Burst, Precharge
L L L HX
REFA
ILLEGAL
LL
READ H X
with Auto L H
Precharge L H
L
L
Op-Code,
Mode-Add
X XX
H HX
H L BA
MRS
DESEL
NOP
TERM
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
L H L H BA, CA, A10 READ / READA Support Concurrent Auto-Precharge 6
L H L L BA, CA, A10 WRITE / WRITEA Support Concurrent Auto-Precharge 6
L L H H BA, RA
ACT
Bank Active / ILLEGAL
2, 6
L L H L BA, A10 PRE / PREA
Precharge / ILLEGAL
2, 6
L L L HX
REFA
ILLEGAL
LL
WRITE H X
with Auto L H
Precharge L H
L
L
Op-Code,
Mode-Add
X XX
H HX
H L BA
MRS
DESEL
NOP
TERM
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
L H L H BA, CA, A10 READ / READA Support Concurrent Auto-Precharge 6
L H L L BA, CA, A10 WRITE / WRITEA Support Concurrent Auto-Precharge 6
L L H H BA, RA
ACT
Bank Active / ILLEGAL
2, 6
L L H L BA, A10 PRE / PREA
Precharge / ILLEGAL
2, 6
L L L HX
REFA
ILLEGAL
LL
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Revision 1.1
Page 10 / 40
Jul., 2013
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet A3S56D30GTP.PDF ] |
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A3S56D30GTP | 256M Double Data Rate Synchronous DRAM | Zentel |
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