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PDF AD5248 Data sheet ( Hoja de datos )
| Número de pieza | AD5248 | |
| Descripción | Dual 256-Position I2C Compatible Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Dual, 256-Position, I2C-Compatible
Digital Potentiometers
AD5243/AD5248
FEATURES
2-channel, 256-position potentiometers
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact 10-lead MSOP (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typical on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1 (AD5248 only)
Computer software replaces microcontroller in factory
programming applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA maximum
Wide operating temperature: −40°C to +125°C
Evaluation board available
APPLICATIONS
Systems calibrations
Electronics level settings
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5243 and AD5248 provide a compact 3 mm × 4.9 mm
packaged solution for dual, 256-position adjustment applications.
The AD5243 performs the same electronic adjustment function as
a 3-terminal mechanical potentiometer, and the AD5248 performs
the same adjustment function as a 2-terminal variable resistor.
Available in four end-to-end resistance values (2.5 kΩ, 10 kΩ,
50 kΩ, and 100 kΩ), these low temperature coefficient devices
are ideal for high accuracy and stability-variable resistance
adjustments. The wiper settings are controllable through the
I2C-compatible digital interface. The AD5248 has extra package
address decode pins, AD0 and AD1, allowing multiple parts to
share the same I2C, 2-wire bus on a PCB. The resistance between
FUNCTIONAL BLOCK DIAGRAMS
A1 W1 B1
A2 W2 B2
VDD
GND
SDA
SCL
WIPER
REGISTER 1
WIPER
REGISTER 2
AD5243
PC INTERFACE
Figure 1. AD5243
W1 B1
W2
B2
VDD
GND
AD0
AD1
SDA
SCL
RDAC
REGISTER 1
RDAC
REGISTER 2
ADDRESS
/DECODE
8
AD5248
SERIAL INPUT
REGISTER
Figure 2. AD5248
the wiper and either endpoint of the fixed resistor varies linearly
with respect to the digital code transferred into the RDAC latch.1
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 6 µA allows the AD5243/AD5248 to be used in portable
battery-operated applications.
For applications that program the AD5243/AD5258 at the factory,
Analog Devices, Inc., offers device programming software running
on Windows® NT/2000/XP operating systems. This software
effectively replaces the need for external I2C controllers, which
in turn enhances the time to market of systems. An AD5243/
AD5248 evaluation kit and software are available. The kit includes
a cable and instruction manual.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
AD5243/AD5248
TIMING CHARACTERISTICS: ALL VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency
Bus-Free Time Between Stop and Start, tBUF
Hold Time (Repeated Start), tHD;STA
Low Period of SCL Clock, tLOW
High Period of SCL Clock, tHIGH
Setup Time for Repeated Start Condition, tSU;STA
Data Hold Time, tHD;DAT2
Data Setup Time, tSU;DAT
Fall Time of Both SDA and SCL Signals, tF
Rise Time of Both SDA and SCL Signals, tR
Setup Time for Stop Condition, tSU;STO
Symbol Conditions
fSCL
t1
t2 After this period, the first clock pulse is
generated.
t3
t4
t5
t6
t7
t8
t9
t10
1 See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 45 to Figure 48).
2 The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Min Typ
0
1.3
0.6
1.3
0.6
0.6
100
0.6
Max Unit
400 kHz
μs
μs
μs
μs
μs
0.9 μs
ns
300 ns
300 ns
μs
SCL
t2
SDA
t1
PS
t8 t6 t9
t3
t8 t9
t4
t7
t2
t5
S
Figure 3. I2C Interface Detailed Timing Diagram
t10
P
Rev. B | Page 5 of 20
5 Page 
Data Sheet
10
TA = 25°C
1
VDD = 5.5V
0.1
VDD = 2.7V
0.01
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIGITAL INPUT VOLTAGE (V)
Figure 24. Supply Current vs. Digital Input Voltage
AD5243/AD5248
VW2
VW1
Figure 27. Analog Crosstalk
VW
SCL
Figure 25. Digital Feedthrough
VW
Figure 28. Midscale Glitch, Code 0x80 to Code 0x7F
VW2
VW1
Figure 26. Digital Crosstalk
VW
SCL
Figure 29. Large-Signal Settling Time
Rev. B | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD5248.PDF ] | |
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