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PDF MC74HC390 Data sheet ( Hoja de datos )
| Número de pieza | MC74HC390 | |
| Descripción | Dual 4-Stage Binary Ripple Counter | |
| Fabricantes | ON Semiconductor | |
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MC74HC390
Dual 4−Stage Binary
Ripple Counter with
÷ 2 and ÷ 5 Sections
High−Performance Silicon−Gate CMOS
The MC54/74HC390 is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit counters, each
composed of a divide−by−two and a divide−by−five section. The
divide−by−two and divide−by−five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
Flip−flops internal to the counters are triggered by high−to−low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4−bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
1, 15
CLOCK A
÷2
COUNTER
3, 13 QA
CLOCK B 4, 12
÷5
COUNTER
5, 11
QB
6, 10
7, 9
QC
QD
RESET 2, 14
PIN 16 = VCC
PIN 8 = GND
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 7
1
http://onsemi.com
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620−10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648−08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B−05
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
CLOCK Aa
RESET a
QAa
CLOCK Ba
QBa
QCa
QDa
GND
1
2
3
4
5
6
7
8
16 VCC
15 CLOCK Ab
14 RESET b
13 QAb
12 CLOCK Bb
11 QBb
10 QCb
9 QDb
FUNCTION TABLE
Clock
AB
Reset Action
XX
X
X
H Reset
÷ 2 and ÷ 5
L Increment
÷2
L Increment
÷5
Publication Order Number:
MC74HC390/D
1 page  
MC74HC390
EXPANDED LOGIC DIAGRAM
CLOCK A 1, 15
CQ
DRQ
3, 13 QA
CLOCK B 4, 12
CQ
DQ
R
5, 11 QB
CQ
DQ
R
6, 10 QC
RESET 2, 14
C
DRQ
7, 9 QD
TIMING DIAGRAM
(QA Connected to Clock B)
0 1 2 3 4 5 6 78 90 1 2 3 4 5 6
CLOCK A
RESET
QA
QB
QC
QD
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MC74HC390.PDF ] | |
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