파트넘버.co.kr 78P2352 데이터시트 PDF


78P2352 반도체 회로 부품 판매점

Dual Channel OC-3/ STM1-E/ E4 LIU



Teridian Semiconductor 로고
Teridian Semiconductor
78P2352 데이터시트, 핀배열, 회로
DESCRIPTION
The 78P2352 is Teridian’s second generation Line
Interface Unit (LIU) for 155 Mbps SDH/SONET
(OC-3, STS-3, or STM-1) and 140 Mbps PDH (E4)
telecom interfaces. The device is a dual channel,
single chip solution that includes an integrated CDR
in the transmit path for flexible NRZ to CMI
conversion. The device can interface to 75coaxial
cable using CMI coding or directly to a fiber optics
transceiver module using NRZ coding. The
78P2352 is compliant with all respective ANSI, ITU-
T, and Telcordia standards for jitter tolerance,
generation, and transfer.
APPLICATIONS
Central Office Interconnects
DSLAMs
Add Drop Multiplexers (ADMs)
Multi Service Switches
Digital Microwave Radios
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
DATA SHEET
SEPTEMBER 2006
FEATURES
ITU-T G.703 compliant cable driver for 139.264
Mbps or 155.52 Mbps CMI-coded coax
transmission
Integrated adaptive CMI equalizer and CDR in
receive path handles over 12.7dB of cable loss
Serial, LVPECL system interface with integrated
CRU in transmit path for flexible NRZ to CMI
conversion.
4-bit parallel CMOS system interface with
master and slave Tx clock modes.
Selectable LVPECL compatible NRZ media
interface for 155.52 Mbps optical transmission.
Configurable via HW control pins or 4-wire serial
port interface
Compliant with ANSI T1.105.03-1994; ITU-T
G.751, G.813, G.823, G.825, G.958; and
Telcordia GR-253-CORE for jitter performance.
Receiver Loss of Signal (LOS) detection
compatible with ITU-T G.783
Operates from a single 3.3V supply
Standard and thermally enhanced 128-pin
JEDEC LQFP package options
BLOCK DIAGRAM
SIxDP/N
SIxCKP/N
PIxCK
PIx[3:0]D
PTOxCK
Lock Detect
Tx CDR
EACH CHANNEL: Tx
FIFO
CMI
Encoder
PMOD, SMOD[1:0], PAR
RLBK
ECLxP/N
TXxCKP/N
CMIxP/N
SOxCKP/N
SOxDP/N
POx[3:0]D
POxCK
CMI
Decoder
Rx CDR
Lock Detect
CMI
EACH CHANNEL: Rx
Adaptive
Eq.
LOS Detect
LLBK
RXxP/N
Page: 1 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4


78P2352 데이터시트, 핀배열, 회로
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
TABLE OF CONTENTS ................................................................................................ 2
FUNCTIONAL DESCRIPTION........................................................................................ 4
MODE SELECTION................................................................................................................................4
REFERENCE CLOCK ............................................................................................................................4
RECEIVER OPERATION .......................................................................................................................4
Receiver Monitor Mode ..................................................................................................................4
Receive Loss of Signal ..................................................................................................................5
Receive Loss of Lock.....................................................................................................................5
TRANSMITTER OPERATION ................................................................................................................5
Synchronous (Re-timing) Tx Serial Modes ..................................................................................5
Plesiochronous Serial Modes .......................................................................................................6
Synchronous Parallel Modes ........................................................................................................6
Transmit FIFO Description ............................................................................................................6
Transmit Driver ...............................................................................................................................7
Clock Synthesizer...........................................................................................................................7
Transmit Backplane Equalizer ......................................................................................................7
Transmit Loss of Lock ...................................................................................................................7
POWER-DOWN FUNCTION .................................................................................................................7
ANALOG LOOPBACK MODES.............................................................................................................7
POWER-ON RESET ..............................................................................................................................7
SERIAL CONTROL INTERFACE .........................................................................................................8
PROGRAMMABLE INTERRUPTS ........................................................................................................8
REGISTER DESCRIPTION............................................................................................. 9
REGISTER ADDRESSING.....................................................................................................................9
REGISTER TABLE.................................................................................................................................9
LEGEND ...............................................................................................................................................10
GLOBAL REGISTERS .........................................................................................................................10
ADDRESS 0-0: MASTER CONTROL REGISTER .......................................................................10
ADDRESS 0-1: INTERRUPT CONTROL REGISTER..................................................................11
PORT-SPECIFIC REGISTERS ............................................................................................................12
ADDRESS N-0: MODE CONTROL REGISTER...........................................................................12
ADDRESS N-1: SIGNAL CONTROL REGISTER ........................................................................13
ADDRESS N-2: ADVANCED TX CONTROL REGISTER 1 ........................................................14
ADDRESS N-3: ADVANCED TX CONTROL REGISTER 0 ........................................................14
ADDRESS N-4: MODE CONTROL REGISTER 2........................................................................14
ADDRESS N-5: STATUS MONITOR REGISTER ........................................................................15
PIN DESCRIPTION ....................................................................................................... 16
LEGEND ...............................................................................................................................................16
TRANSMITTER PINS ...........................................................................................................................16
RECEIVER PINS ..................................................................................................................................17
REFERENCE AND STATUS PINS ......................................................................................................18
CONTROL PINS ..................................................................................................................................19
SERIAL-PORT PINS ............................................................................................................................21
POWER AND GROUND PINS .............................................................................................................21
Page: 2 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4




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