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PDF 74LS163A Data sheet ( Hoja de datos )
| Número de pieza | 74LS163A | |
| Descripción | BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74LS163A (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous count-
ers. They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency division and
other applications. The LS160A and LS162A count modulo 10 (BCD). The
LS161A and LS163A count modulo 16 (binary.)
The LS160A and LS161A have an asynchronous Master Reset (Clear)
input that overrides, and is independent of, the clock and all other control
inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that
overrides all other control inputs, but is active only during the rising clock
edge.
BCD (Modulo 10)
Binary (Modulo 16)
Asynchronous Reset
LS160A
LS161A
Synchronous Reset
LS162A
LS163A
• Synchronous Counting and Loading
• Two Count Enable Inputs for High Speed Synchronous Expansion
• Terminal Count Fully Decoded
• Edge-Triggered Operation
• Typical Count Rate of 35 MHz
• ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9
1234
*R CP P0 P1
56
78
P2 P3 CEP GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
*MR for LS160A and LS161A
*SR for LS162A and LS163A
PIN NAMES
PE
P0 – P3
CEP
CET
CP
MR
SR
Q0 – Q3
TC
Parallel Enable (Active LOW) Input
Parallel Inputs
Count Enable Parallel Input
Count Enable Trickle Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Synchronous Reset (Active LOW) Input
Parallel Outputs (Note b)
Terminal Count Output (Note b)
LOADING (Note a)
HIGH
LOW
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
10 U.L.
10 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS160A
SN54/74LS161A
SN54/74LS162A
SN54/74LS163A
BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
934 56
PE P0 P1 P2 P3
7 CEP
10 CET
TC 15
2 CP
*R Q0 Q1 Q2 Q3
1 14 13 12 11
VCC = PIN 16
GND = PIN 8
*MR for LS160A and LS161A
*SR for LS162A and LS163A
FAST AND LS TTL DATA
5-278
1 page  
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
tWCP
Clock Pulse Width Low
tW MR or SR Pulse Width
ts Setup Time, other*
ts Setup Time PE or SR
th Hold Time, data
th Hold Time, other
trec Recovery Time MR to CP
*CEP, CET or DATA
Limits
Min Typ Max
25
20
20
25
3
0
15
Unit
ns
ns
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time re-
quired between the end of the reset pulse and the clock transi-
tion from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
AC WAVEFORMS
CP
Q
tW(H)
1.3 V
tW(L)
tPHL
1.3 V
1.3 V
tPLH
OTHER CONDITIONS:
PE = MR (SR) = H
CEP = CET = H
1.3 V
Figure 1. Clock to Output Delays, Count
Frequency, and Clock Pulse Width
MR 1.3 V
tW
CP
⋅ ⋅ ⋅Q0 Q1 Q2 Q3
tPHL
trec
1.3 V
OTHER CONDITIONS:
PE = L
P0 = P1 = P2 = P3 = H
1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
FAST AND LS TTL DATA
5-282
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74LS163A.PDF ] | |
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