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PDF zDA14580 Data sheet ( Hoja de datos )
| Número de pieza | zDA14580 | |
| Descripción | Low Power Bluetooth Smart SoC | |
| Fabricantes | Dialog Semiconductor | |
| Logotipo |  |
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DATASHEET - FINAL
DA14580
Low Power Bluetooth Smart SoC
JANUARY 29, 2015 V3.1
General description
84 kB ROM
The DA14580 integrated circuit has a fully integrated
radio transceiver and baseband processor for Blue-
tooth® Smart. It can be used as a standalone applica-
tion processor or as a data pump in hosted systems.
8 kB Retention SRAM
Power management
Integrated Buck/Boost DC-DC converter
P0, P1, P2 and P3 ports with 3.3 V tolerance
Easy decoupling of only 4 supply pins
The DA14580 supports a flexible memory architecture
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
for storing Bluetooth profiles and custom application
battery cells
code, which can be updated over the air (OTA). The
10-bit ADC for battery voltage measurement
qualified Bluetooth Smart protocol stack is stored in a
dedicated ROM. All software runs on the ARM® Cor-
tex®-M0 processor via a simple scheduler.
Digital controlled oscillators
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
The Bluetooth Smart firmware includes the L2CAP ser-
vice layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT)
and the Generic Access Profile (GAP). All profiles pub-
lished by the Bluetooth SIG as well as custom profiles
are supported.
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
General purpose I/Os: 14 (WLCSP34 package),
24 (QFN40 package), 32 (QFN48 package)
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
The transceiver interfaces directly to the antenna and
I2C bus at 100 kHz, 400 kHz
is fully compliant with the Bluetooth 4.1 standard.
3-axes capable Quadrature Decoder
The DA14580 has dedicated hardware for the Link
Layer implementation of Bluetooth Smart and interface
controllers for enhanced connectivity capabilities.
Analog interfaces
4-channel 10-bit ADC
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
Features
Single wire antenna: no RF matching or RX/TX
switching required
Complies with Bluetooth V4.1, ETSI EN 300 328 and
Supply current at VBAT3V:
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
(US) and ARIB STD-T66 (Japan)
0 dBm transmit output power
Processing power
-20 dBm output power in “Near Field Mode”
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
-93 dBm receiver sensitivity
face Packages:
Dedicated Link Layer Processor
WLCSP 34 pins, 2.436 mm x 2.436 mm
AES-128 bit encryption Processor
QFN 40 pins, 5 mm x 5 mm
Memories
QFN 48 pins, 6 mm x 6 mm
32 kB One-Time-Programmable (OTP) memory
KGD (wafer, dice)
42 kB System SRAM
________________________________________________________________________________________________
System diagram
© 2014 Dialog Semiconductor
1 www.dialog-semiconductor.com
1 page  
P0_0
P0_1
P0_2
P0_3
NC
P0_4
P0_5
P2_1
P0_6
P0_7
1
2
3
4
5
6
7
8
9
10
DA14580
(Top View)
30 XTAL16Mm
29 XTAL16Mp
28 P1_3
27 P1_2
26 SW_CLK
25 SWDIO
24 P1_1
23 VBAT1V
22 P1_0
21 SWITCH
Pin 0: GND
plane
Figure 4 QFN40 pin assignment
Table 1: Ordering information (samples)
Part number
DA14580-01UNA
DA14580-01A31
DA14580-01AT1
Package
WLSCP34
QFN48
QFN40
Size (mm)
2.436 x 2.436
6x6
5x5
Shipment form
Mini-reel
Tray
Tray
Pack quantity
50/100/1000
50
50
Table 2: Ordering information (production)
Part number
DA14580-01UNA
DA14580-01A32
DA14580-01AT2
DA14580-01WO4
DA14580-01WC4
Package
WLSCP34
QFN48
QFN40
KGD
KGD
Size (mm)
2.436 x 2.436
6x6
5x5
wafer
dice
Shipment form
Pack quantity
Mini-reel
5000
Reel
4000
Reel
5000
Contact Dialog Semiconductor sales office
Contact Dialog Semiconductor sales office
© 2014 Dialog Semiconductor 5 Final - January 29, 2015 v3.1
5 Page 
Application
Accelerometer SPI FLASH
Driver
Driver
GPIO
Driver
SPI
Driver
EEPROM
I2C
Driver
UART
Driver
Battery
Driver
Sample
Drivers
CORE
Drivers
ADC
Driver
Quadrature
Timers
Figure 6 Hardware abstraction layer
Core drivers are provided for each interface of the
DA14580 enabling optimized usage of the hardware’s
capabilities. These drivers provide an easy-to-use
interface towards the hardware engines without having
to interfere with the register programming directly.
On top of the core drivers, a number of sample drivers
is also provided enabling communication with basic
Bluetooth Smart application components: accelerome-
ters, FLASH/EEPROM non-volatile memories, etc.
3.3 MEMORIES
The following memories are part of the DA14580’s
internal blocks:
ROM. This is a 84 kB ROM containing the Bluetooth
Smart protocol stack as well as the boot code
sequence.
OTP. This is a 32 kB One-Time Programmable mem-
ory array, used to store the application code as well as
Bluetooth Smart profiles. It also contains the system
configuration and calibration data.
System SRAM. This is a 42 kB system SRAM (Sys-
RAM) which is primarily used for mirroring the program
code from the OTP when the system wakes/powers
up. It also serves as Data RAM for intermediate varia-
bles and various data that the protocol requires.
Optionally, it can be used as extra memory space for
the BLE TX and RX data structures.
Retention RAMs. These are 4 special low leakage
SRAM cells (2 kB + 2 kB + 3 kB + 1 kB) used to store
various data of the Bluetooth Smart protocol as well as
the system’s global variables and processor stack
when the system goes into Deep Sleep mode. Storage
of this data ensures secure and quick configuration of
the BLE Core after the system wakes up. Every cell
can be powered on or off according to the application
needs for retention area when in Deep Sleep mode.
3.4 FUNCTIONAL MODES
The DA14580 is optimized for deeply embedded appli-
cations such as health monitoring, sports measuring,
human interaction devices etc. Customers are able to
develop and test their own applications. Upon comple-
tion of the development, the application code can be
programmed into the OTP. In general, the system has
three functional modes of operation:
A. Development mode: During this phase application
code is developed using the ARM Cortex-M0 SW envi-
ronment. The compiled code is then downloaded into
the System RAM or any Retention RAMs by means of
SWD (JTAG) or any serial interface (e.g. UART).
Address 0x00 is remapped to the physical memory that
contains the code and the CPU is configured to reset
and execute code from the remapped device. This
mode is enabling application development, debugging
and on-the-fly testing.
B. Normal mode: After the application is ready and
verified, the code can be burned into the OTP. When
the system boots/wakes up, the DMA of the OTP con-
troller will automatically copy the program code from
the OTP into the system RAM. Next, a SW reset or a
jump to the System RAM occurs and code execution is
started. Hence, in this mode, the system is autono-
mous, contains the required SW in OTP and is ready
for integration into the final product.
C. Calibration mode: Between Development and Nor-
mal mode, there is an intermediate stage where the
chip needs to be calibrated with respect to two impor-
tant features:
• Programming of the Bluetooth device address
• Programming of the trimming value for the external
16 MHz crystal.
This mode of operation applies to the final product and
is performed by the customer. During this phase, cer-
© 2014 Dialog Semiconductor 11 Final - January 29, 2015 v3.1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet zDA14580.PDF ] | |
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