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PDF JS29F08G08CANB2 Data sheet ( Hoja de datos )
| Número de pieza | JS29F08G08CANB2 | |
| Descripción | SD74 NAND Flash Memory | |
| Fabricantes | Intel | |
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Intel® SD74 NAND Flash Memory
JS29F04G08AANB1, JS29F08G08CANB2, JS29F16G08FANB1
Product Features
Datasheet
Single-level cell (SLC) Technology
Organization:
— Page size:
x8: 2,112 bytes (2,048 + 64 bytes)
— Block size: 64 pages (128K + 4K bytes)
— Plane size: 2,048 blocks
— Device size: 4Gb: 4,096 blocks; 8Gb: 8,192
blocks; 16Gb: 16,384 blocks
Read performance:
— Random read: 25µs (MAX)
— Sequential read: 25ns (MIN)
Write performance:
— Page program: 220µs (TYP)
Block erase: 1.5ms (TYP)
Data Retention:
— 10 years
Endurance:
— 100,000 PROGRAM/ERASE cycles
First block (block address 00h):
— Guaranteed to be valid up to 1,000
PROGRAM/ERASE cycles
Vcc:
— 2.7V – 3.6V
Operating Temperature:
— -25 oC to 85 oC
Command set:
— Industry-standard basic NAND Flash
command set
Advanced Command Set:
— Two-plane commands
— Interleaved die operation
— READ UNIQUE ID (contact factory)
— Internal Data Move: Operations supported
within the plane from which data is read
Operation status byte:
— Provides software method for detecting:
— Operation completion
— Pass/fail condition
— Write-protect status
Ready/busy# (R/B#) signal:
— Provides a hardware method for detecting
PROGRAM or ERASE cycle completion
WP# signal:
— Write protect entire device
RESET:
— Required after power-up
Package Types:
— 48-pin TSOP Type 1
Configuration:
# of Die
1
2
4
# of CE# # of R/B#
11
22
22
I/O
Common
Common
Common
Order Number: 312774-012US
March 2007
1 page  
Intel® SD74 NAND Flash Memory
Revision History
Date
Revision Description
March 2007
012 • Added missing Test Conditions table.
February 2007
011
• Changed comment for the NVB spec for the 16Gb device. Edited some typos in rev 010.
• Deleted line item JS29F08G08CANB1.
February 2007
010
• Added notes about 81H in second command cycle of dual plane program operations in Section
7.7.4, “TWO-PLANE PROGRAM PAGE 80h-11h-80h-10h or 80h-11h-81h-10h” on page 41.
November 2006 009
• Updated the Table 20, “Intel® NAND Flash Memory Ordering Information” on page 69.
• Deleted the OCPL figure in the package section.
13-Sep-06
• Updated the R/B# and R/B2# description in Section 3.0, “Signal Assignments and
008 Descriptions” on page 11.
• Updated the part number decoder in Section 10.0, “Ordering Information” on page 69.
8-Sep-06
• Added configuration table to title page.
• Updated the ordering information and part number decoder in Section 10.0, “Ordering
007 Information” on page 69.
• Changed the 8 Gb part number from JS29F08G08BANB1 to JS29F08G08CANB1 throughout the
document to reflect the change to 2 CEs.
22-Aug-06
• Updated document to reflect 2 CE#s for the dual-die package device.
• Section 7.2.4, “READ ID 90h” on page 27: Revised description.
• Package diagrams have been updated.
• Figure 1, “Intel® SD74 NAND Flash Memory Functional Block Diagram” on page 7: Added “(2
planes)” to the NAND Flash Array.
• Table 16, “Two-Plane Command Set” on page 25: Deleted “MULTIPLE-DIE READ STATUS” from
command 06h and updated note 3.
• Section 7.7.2, “TWO-PLANE PAGE READ 00h-00h-30h” on page 39: Updated the fourth
paragraph.
• Section 7.7.10, “TWO-PLANE/MULTIPLE-DIE READ STATUS 78h” on page 47: Updated first
006 paragraph and added a new paragraph at the end of the section.
• Section 7.8, “Interleaved Die Operations” on page 48: Updated final paragraph.
• Section 7.9.1, “RESET FFh” on page 54: Added “to all CE#s” and “and OTP operations” to the
last paragraph.
• Section 6.1, “Vcc Power Cycling” on page 19: Changed 1ms to 10µs in first paragraph; added
“to all CE#s” in last paragraph.
• Figure 13, “AC Waveforms During Power Transitions” on page 20: Updated WE# signal.
• Table 14, “PROGRAM/ERASE Characteristics” on page 23: Added note 4.
• Figure 36, “TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle” on page 48: Added figure
showing all timing parameters.
• Section 4.0, “Package Information” on page 13: Inserted recently updated versions of package
diagrams.
1-Aug-06
Updated the Operating Temperature range.
005
Updated with new product naming convention, and document title change.
29-Jun-06
004 Corrected typos in Section 6.0, “Electrical Characteristics”.
15-Jun-06
The maximum number of programming operations before an erase is required has been reduced
003 from 8 to 4. This change is reflected in Table 14, “PROGRAM/ERASE Characteristics” on page 23 in
the Electrical Characteristics chapter and Section 7.3.1, “PROGRAM PAGE 80h–10h” on page 31.
02-Jun-06
• Adjusted Product Features section on page 1, including Write Performance Page Program
values from to
002 • Adjusted electrical specifications. See Section 6.0, “Electrical Characteristics” on page 19 and
the product features section on page 1.
• Changes to Section 7.0, “Command Definitions” on page 24.
March 2006
001 • Initial Release.
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Datasheet
5
5 Page 
Intel® SD74 NAND Flash Memory
3.0 Signal Assignments and Descriptions
Figure 5.
Table 4.
Signal Assignment (Top View) 48-Pin TSOP
x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
Vcc
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1●
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
x8
48 DNU
47 NC
46 NC
45 NC
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 NC
39 NC
38 DNUorVss
37 Vcc
36 Vss
35 NC
34 NC
33 NC
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 NC
27 NC
26 DNU
25 DNU
Note:
1. CE2# and R/B2# are available on 8Gb and 16Gb devices only. These pins are NC for other
configurations.
Signal Descriptions (Sheet 1 of 2)
Symbol
ALE
CE#, CE2#
CLE
RE#
WE#
Type
Input
Input
Input
Input
Input
Description
Address latch enable: During the time ALE is HIGH, address information is
.transferred from I/O[7:0] into the on-chip address register on the rising
edge of WE# When address information is not being loaded, ALE should
be driven LOW.
Chip enable: Gates transfers between the host system and the NAND Flash
device. After the device starts a PROGRAM or ERASE operation, CE# can
be de-asserted. For the 8Gb configuration, CE# controls the first 4Gb of
memory; CE2# controls the second 4Gb of memory. For the 16Gb
configuration, CE# controls the first 8Gb of memory; CE2# controls the
second 8Gb. See the Bus Operation section, starting on page 14, for
additional operational details.
Command latch enable: When CLE is HIGH, information is transferred from
I/O[7:0] to the on-chip command register on the rising edge of WE#.
When command information is not being loaded, CLE should be driven
LOW.
Read enable: Gates transfers from the NAND Flash device to the host
system.
Write enable: Gates transfers from the host system to the NAND Flash
device.
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Datasheet
11
11 Page | ||
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