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PDF LF1745 Data sheet ( Hoja de datos )

Número de pieza LF1745
Descripción LCD Display
Fabricantes LITEMAX 
Logotipo LITEMAX Logotipo



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No Preview Available ! LF1745 Hoja de datos, Descripción, Manual

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LITEMAX LF1745
Sunlight Readable 17" LCD Display
(1st Edition 4/9/2004 )
All information is subject to change without notice.
LITEMAX Electronics Inc.
4F, No.131-3, Lane235, Bau-chiau Rd.,
Shin-dian City, Taipei County, Taiwan R.O.C.
Tel : 886-2-8919-1858
Fax: 886-2-8919-1300
Homepage: http://www.litemax.com.tw
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LF1745 pdf
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Functional Block Diagram
The following diagram shows the functional block of the 17.0 inches Color TFT-LCD Module:
L VDS
+ 5V
G1
G1024
T F T -L CD
1280*(3)*1024
P ixels
X-Driver IC
D3840
10 CCF L
DC P OW E R
Inver ter
LF1745
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LF1745 arduino
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Signal Description
The module using a pair of LVDS receiver SN75LVDS82 (Texas Instruments) or compatible. LVDS is a
differential signal technology for LCD interface and high speed data transfer device. Transmitter shall be
SN75LVDS83(negative edge sampling) or compatible. The first LVDS port(RxOxxx) transmits odd pixels while
the second LVDS port(RxExxx) transmits even pixels.
PIN # SIGNAL NAME
DESCRIPTION
1 RxO0-
Negative LVDS differential data input (Odd data)
2 RxO0+
Positive LVDS differential data input (Odd data)
3 RxO1-
Negative LVDS differential data input (Odd data)
4 RxO1+
5 RxO2-
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Odd data, H-Sync,V-Sync,DSPTMG)
6 RxO2+
7 GND
Positive LVDS differential data input (Odd data, H-Sync,V-Sync,DSPTMG)
Power Ground
8 RxOC-
Negative LVDS differential clock input (Odd clock)
9 RxOC+
Positive LVDS differential clock input (Odd clock)
10 RxO3-
11 RxO3+
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
12 RxE0-
13 RxE0+
Negative LVDS differential data input (Even clock)
Positive LVDS differential data input (Even data)
14 GND
Power Ground
15 RxE1-
Positive LVDS differential data input (Even data)
16 RxE1+
17 GND
Negative LVDS differential data input (Even data)
Power Ground
18 RxE2-
Negative LVDS differential data input (Even data)
19 RxE2+
20 RxEC-
Positive LVDS differential data input (Even data)
Negative LVDS differential clock input (Even clock)
21 RxEC+
22 RxE3-
Positive LVDS differential clock input (Even clock)
Negative LVDS differential data input (Even data)
23 RxE3+
Positive LVDS differential data input (Even data)
24 GND
Power Ground
25 NC
26 NC
-
-
27 NC
-
28 POWER
Power
29 POWER
30 POWER
Power
Power
Note: Input signals of odd and even clock shall be the same timing.
LVDS DATA Name
Description
DSP
Display Timing: When the signal is high, the pixel data shall be valid to be displayed
V-S Vertical Sync: Both Positive and Negative polarity are acceptable
H-S Horizontal Sync: Both Positive and Negative polarity are acceptable
LF1745
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