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P15NK50ZFP 반도체 회로 부품 판매점

STP15NK50ZFP



STMicroelectronics 로고
STMicroelectronics
P15NK50ZFP 데이터시트, 핀배열, 회로
STP15NK50Z/FP, STB15NK50Z
STB15NK50Z-1, STW15NK50Z
N-CHANNEL500V-0.30-14ATO-220/FP/D2PAK/I2PAK/TO-247
Zener-Protected SuperMESH™Power MOSFET
TYPE
VDSS RDS(on)
ID
Pw
STP15NK50Z
STP15NK50ZFP
STB15NK50Z
STB15NK50Z-1
STW15NK50Z
500 V
500 V
500 V
500 V
500 V
< 0.34
< 0.34
< 0.34
< 0.34
< 0.34
14 A
14 A
14 A
14 A
14 A
160 W
40 W
160 W
160 W
160 W
s TYPICAL RDS(on) = 0.30
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s GATE CHARGE MINIMIZED
s VERY LOW INTRINSIC CAPACITANCES
s VERY GOOD MANUFACTURING
REPEATIBILITY
TO-220
123
I2PAK
3
2
1
TO-220FP
3
2
1
TO-247
3
1
D2PAK
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established strip-
based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is tak-
en to ensure a very good dv/dt capability for the
most demanding applications. Such series comple-
ments ST full range of high voltage MOSFETs in-
cluding revolutionary MDmesh™ products.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
s LIGHTING
INTERNAL SCHEMATIC DIAGRAM
ORDERING INFORMATION
SALES TYPE
MARKING
STP15NK50Z
P15NK50Z
STP15NK50ZFP
P15NK50ZFP
STB15NK50ZT4
B15NK50Z
STB15NK50Z
B15NK60Z
STB15NK50Z-1
STW15NK50Z
B15NK50Z
W15NK50Z
PACKAGE
TO-220
TO-220FP
D2PAK
D2PAK
I2PAK
TO-247
PACKAGING
TUBE
TUBE
TAPE & REEL
TUBE
(ONLY UNDER REQUEST)
TUBE
TUBE
August 2002
1/14


P15NK50ZFP 데이터시트, 핀배열, 회로
STP15NK50Z, STP15NK50ZFP, STB15NK50Z, STB15NK50Z-1, STW15NK50Z
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
VDGR
Drain-gate Voltage (RGS = 20 k)
VGS Gate- source Voltage
ID Drain Current (continuous) at TC = 25°C
ID Drain Current (continuous) at TC = 100°C
IDM ( ) Drain Current (pulsed)
PTOT
Total Dissipation at TC = 25°C
Derating Factor
IGS Gate-source Current (DC)
VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ)
dv/dt (1) Peak Diode Recovery voltage slope
VISO
Insulation Withstand Voltage (DC)
Tj Operating Junction Temperature
Tstg Storage Temperature
( ) Pulse width limited by safe operating area
(1) ISD 14A, di/dt 200A/µs, VDD V(BR)DSS, Tj TJMAX.
(*) Limited only by maximum temperature allowed
STP15NK50Z
STB15NK50Z
STB15NK50Z-1
14
8.8
56
160
1.28
-
Value
STP15NK50ZFP STW15NK50Z
500
500
± 30
14 (*)
8.8 (*)
56 (*)
40
0.32
± 20
4000
4.5
2500
-55 to 150
-55 to 150
14
8.8
56
160
1.28
-
Unit
V
V
V
A
A
A
W
W/°C
mA
V
V/ns
V
°C
°C
THERMAL DATA
TO-220
I2PAK
D2PAK
TO-220FP
TO-247
Rthj-case Thermal Resistance Junction-case Max
0.78 3.1 0.78 °C/W
Rthj-pcb Thermal Resistance Junction-pcb Max (#)
60
°C/W
Rthj-amb Thermal Resistance Junction-ambient Max
62.5 50 °C/W
Tl Maximum Lead Temperature For Soldering Purpose
300
°C
AVALANCHE CHARACTERISTICS
Symbol
Parameter
IAR Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
EAS Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
Max Value
14
300
Unit
A
mJ
GATE-SOURCE ZENER DIODE
Symbol
Parameter
BVGSO
Gate-Source Breakdown
Voltage
(#) When mounted on minimum Footprint
Test Conditions
Igs=± 1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/14




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