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PDF M25P80 Data sheet ( Hoja de datos )
| Número de pieza | M25P80 | |
| Descripción | 8Mb (1Mb x 8) serial Flash memory device | |
| Fabricantes | Micron | |
| Logotipo |  |
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Micron M25P80 Serial Flash Embedded Memory
Features
Micron M25P80 Serial Flash Embedded
Memory
8Mb, 3V
Features
• SPI bus-compatible serial interface
• 8Mb Flash memory
• 75 MHz clock frequency (maximum)
• 2.7V to 3.6V single supply voltage
• Page program (up to 256 bytes) in 0.64ms (TYP)
• Erase capability
– Sector erase: 512Kb in 0.6 s (TYP)
– Bulk erase: 8Mb in 8 s (TYP)
• Write protection
– Hardware write protection: protected area size
defined by nonvolatile bits BP0, BP1, BP2
• Deep power-down: 1µA (TYP)
• Electronic signature
– JEDEC-standard 2-byte signature (2014h)
– Unique ID code (UID) and 16 bytes of common
Flash interface (CFI) data
– RES command, one-byte signature (13h) for
backward compatibility
• More than 100,000 write cycles per sector
• More than 20 years data retention
• Automotive-grade parts available
• Packages (RoHS-compliant)
– SO8N (MN) 150 mils
– SO8W (MW) 208 mils
– VFDFPN8 (MP) MLP8 6mm x 5mm
– UFDFPN8 (MC) MLP8 4mm x 3mm
PDF: 09005aef84566560
m25p80.pdf - Rev. G 1/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
Micron M25P80 Serial Flash Embedded Memory
Features
List of Tables
Table 1: Signal Names ...................................................................................................................................... 6
Table 2: Signal Descriptions ............................................................................................................................. 8
Table 3: Protected Area Sizes .......................................................................................................................... 12
Table 4: Sectors 15:0 ...................................................................................................................................... 15
Table 5: Command Set Codes ........................................................................................................................ 17
Table 6: READ IDENTIFICATION Data Out Sequence ..................................................................................... 20
Table 7: Status Register Protection Modes ...................................................................................................... 24
Table 8: Power-Up Timing and VWI Threshold ................................................................................................. 35
Table 9: Absolute Maximum Ratings .............................................................................................................. 36
Table 10: Operating Conditions ...................................................................................................................... 36
Table 11: Data Retention and Endurance ........................................................................................................ 36
Table 12: DC Current Specifications ............................................................................................................... 37
Table 13: DC Voltage Specifications ................................................................................................................ 37
Table 14: AC Measurement Conditions ........................................................................................................... 38
Table 15: Capacitance .................................................................................................................................... 38
Table 16: AC Specifications (25 MHz, Device Grade 3, VCC[min]=2.7V) ............................................................. 38
Table 17: Instruction Times (25 MHz, Device Grade 3, VCC[min]=2.7V) ............................................................ 39
Table 18: AC Specifications (75 MHz, Device Grade 3 and 6, VCC[min]=2.7V) .................................................... 40
Table 19: Instruction Times (75 MHz, Device Grade 3 and 6, VCC[min]=2.7V) ................................................... 41
Table 20: Part Number Example ..................................................................................................................... 48
Table 21: Part Number Information Scheme ................................................................................................... 48
Table 22: Part Number Example ..................................................................................................................... 49
Table 23: Part Number Information Scheme ................................................................................................... 49
PDF: 09005aef84566560
m25p80.pdf - Rev. G 1/13 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
5 Page 
Micron M25P80 Serial Flash Embedded Memory
Operating Features
Operating Features
Page Programming
To program one data byte, two commands are required: WRITE ENABLE, which is one
byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by
the internal PROGRAM cycle of duration tPP. To spread this overhead, the PAGE PRO-
GRAM command allows up to 256 bytes to be programmed at a time (changing bits
from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To
optimize timings, it is recommended to use the PAGE PROGRAM command to program
all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM
sequences with each containing only a few bytes.
Sector Erase, Bulk Erase
The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be ach-
ieved a sector at a time using the SECTOR ERASE command, or throughout the entire
memory using the BULK ERASE command. This starts an internal ERASE cycle of dura-
tion tSSE, tSE or tBE. The ERASE command must be preceded by a WRITE ENABLE com-
mand.
Polling during a Write, Program, or Erase Cycle
An improvement in the time to complete the following commands can be achieved by
not waiting for the worst case delay (tW, tPP, tSE, or tBE).
• WRITE STATUS REGISTER
• PROGRAM
• ERASE (SECTOR ERASE, BULK ERASE)
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete.
Active Power, Standby Power, and Deep Power-Down
When chip select (S#) is LOW, the device is selected, and in the ACTIVE POWER mode.
When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER
mode until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS
REGISTER). The device then goes in to the STANDBY POWER mode. The device con-
sumption drops to ICC1.
The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command
is executed. The device consumption drops further to ICC2. The device remains in this
mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in
the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE
commands. This provides an extra software protection mechanism when the device is
not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or
ERASE operations. For further information, see the DEEP POWER DOWN command.
PDF: 09005aef84566560
m25p80.pdf - Rev. G 1/13 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
11 Page | ||
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| PDF Descargar | [ Datasheet M25P80.PDF ] | |
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