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PDF ST92F120 Data sheet ( Hoja de datos )

Número de pieza ST92F120
Descripción 8/16-BIT FLASH MCU
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! ST92F120 Hoja de datos, Descripción, Manual

ST92F120
8/16-BIT FLASH MCU FAMILY
WITH RAM, EEPROM AND J1850 BLPD
DATASHEET
s Memories
– Internal Memory: up to 128 Kbytes Single
Voltage FLASH, 2 to 4 Kbytes RAM, 1K byte
emulated EEPROM (E3PROMTM)
– 224 general purpose registers (register file)
available as RAM, accumulators or index
pointers
s Clock, Reset and Supply Management
PQFP100
– Register-oriented 8/16 bit CORE with RUN,
WFI, SLOW, HALT and STOP modes
– 0-24 MHz Operation (internal Clock), 4.5 - 5.5
Volt voltage range
– PLL Clock Generator (3-5 MHz crystal)
– Min. instruction time: 83 ns (24 MHz int.
clock)
s Interrupt Management
– 77 I/O pins
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or
additional external interrupt with multi-level in-
terrupt handler
s Timers
– 16-bit Timer with 8 bit Prescaler, able to be
used as a Watchdog Timer with a large range
of service time (HW/SW enabling through
dedicated pin)
– 16-bit Standard Timer that can be used to
generate a time base independent of PLL
Clock Generator
s Communication Interfaces
– 2 Serial Communication Interfaces with asyn-
chronous and synchronous capabilities. Soft-
ware Management and synchronous mode
supported
– Serial Peripheral Interface (SPI) with Selecta-
ble Master/Slave mode
– J1850 Byte Level Protocol Decoder (JBLPD)
(on J versions only)
– Full I²C multiple Master/Slave Interface sup-
porting Access Bus
s 8-bit Analog to Digital Converter allowing up
to 16 input channels
s DMA Controller for reduced processor
overhead
s Instruction Set
– Rich Instruction Set with 14 Addressing
Modes
– Division-by-zero trap generation
s Development Tools
– Two 16-bit independent Extended Function
Timers (EFTs) with Prescaler, 2 Input Cap-
tures and two Output Compares
– Two 16-bit Multifunction Timers, with Prescal-
er, 2 Input Captures and 2 Output Compares
– Versatile Development Tools, including As-
sembler, Linker, C-Compiler, Archiver,
Source Level Debugger, Hardware Emulators
and Real Time Operating System
DEVICE SUMMARY
Features
FLASH - bytes
RAM - bytes
E3PROM - bytes
Network Interface
Temp. Range
Packages
ST92F120V9
60K
2K
--
ST92F120JV9
ST92F120V1
1K
J1850
--
-40o C to 105o C or -40oC to 85o C
PQFP100
ST92F120JV1
128K
4K
J1850
Rev. 2.6
September 2002
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1 page




ST92F120 pdf
ST92F120 - GENERAL DESCRIPTION
Figure 1. ST92F120JV: Architectural Block Diagram
FLASH
60/128 Kbytes
Ext. MEM.
ADDRESS
DATA
Port0
A[7:0]
D[7:0]
AS
DS
RW
WAIT
NMI
RW
DS2
INT[6:0]
WKUP[15:0]
OSCIN
OSCOUT
RESET
CLOCK2/8
CLOCK2
INTCLK
STOUT
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
EEPROM
1K byte
RAM
2/4 Kbytes
256 bytes
Register File
8/16 bit
CPU
Interrupt
Management
ST9 CORE
RCCU
ST. TIMER
EF TIMER 0
EF TIMER 1
MF TIMER 0
MF TIMER 1
Ext. MEM.
ADDRESS
Port1
Fully
Prog.
I/Os
J1850
JBLPD
(optional)
I2C BUS
WATCHDOG
SPI
A/D CONV. 0
A/D CONV. 1
SCI 0
SCI 1 *
A[15:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:1]
P4[7:0]
P5[7:0]
P6[5:0]
P7[7:0]
P8[7:0]
P9[7:0]
VPWI
VPWO
SDAI
SDAO
SCLI
SCLO
WDOUT
HW0SW1
WDIN
MISO
MOSI
SCK
SS
A0IN[7:0]
EXTRG
A1IN[7:0]
TXCLK0
RXCLK0
SIN0
DCD0
SOUT0
CLKOUT0
RTS0
TXCLK1
RXCLK1
SIN1
DCD1
SOUT1
CLKOUT1
RTS1
All alternate functions (Italic characters) are mapped on Port2, Port3, Port4, Port5, Port6, Port7, Port8 and Port9
* Available on some versions only
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9

5 Page





ST92F120 arduino
ST92F120 - GENERAL DESCRIPTION
1.2.4.5 Power Supply and Ground
As already said for the I/O pins, in order to guaran-
tee ST9 compliancy with respect to Quality Assur-
ance recommendations concerning ESD and
Latchup, dedicated circuits are added to the differ-
ent power supply and ground pins (digital and an-
alog). These structures create preferred paths for
the high current injected during discharges, avoid-
ing damage to active logic and circuitry. It is impor-
tant for the system designer to take this added cir-
cuitry into account, which is not always transpar-
ent with respect to the relative level of voltages ap-
plied to the different power supply and ground
pins. Figure 6 shows schematically the protection
net implemented on ST9 devices, composed of di-
odes and other special structures.
The clamp structure between the VDD and VSS
pins is designed to be active during very fast tran-
sitions (typical of electrostatic discharges). Other
paths are implemented through diodes: they limit
the possibility of positively differentiating AVDD
and VDD (i.e. AVDD > VDD); similar considerations
are valid for AVSS and VSS due to the back-to-
back diode structure implemented between the
two pins. Anyway, it must be highlighted that, be-
cause VSS and AVSS are connected to the sub-
strate of the silicon die (even though in different ar-
eas of the die itself), they represent the reference
point from which all other voltages are measured,
and it is recommended to never differentiate AVSS
from VSS.
Note: If more than one pair of pins for VSS and
VDD is available on the device, they are connected
internally and the protection net diagram remains
the same as shown in Figure 6.
Figure 6. Power Supply and Ground Configuration
VTEST
VDD
P
P
VSS
AVDD
AVSS
11/324
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