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PDF GD25Q80B Data sheet ( Hoja de datos )
| Número de pieza | GD25Q80B | |
| Descripción | Uniform sector dual and quad serial flash | |
| Fabricantes | ELM | |
| Logotipo |  |
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GD25Q80B
DATASHEET
44 - 1
Rev.1.2
1 page  
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2. GENERAL DESCRIPTION
The GD25Q80B (8M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of
480Mbits/s.
CONNECTION DIAGRAM
CS# 1
8 VCC
SO 2
WP# 3
Top View
7 HOLD#
6 SCLK
VSS 4
5 SI
8–LEAD WSON/USON
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8–LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
PIN DESCRIPTION
Pin Name
I/O
CS# I
SO (IO1)
I/O
WP# (IO2)
I/O
VSS
SI (IO0)
I/O
SCLK
I
HOLD# (IO3)
I/O
VCC
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
5
44 - 5
Rev.1.2
5 Page 
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
GD25Q80BxIGxThe Write Enable Latch (WEL) bit indicUatensitfhoe rstmatussoef cthetoinrterdnaul Walritae nEndablqe uLaatcdh. Wseherniaselt tfola1 sthhe internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, BP0) bits are”000” when CMP=0, or “101/11X”
when CMP=1.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP
Status Register
Description
00X
Software Protected
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
010
Hardware Protected
WP#=0, the Status Register locked and can not be written to.
011
Hardware Unprotected
WP#=1, the Status Register is unlocked and can be written to
after a Write Enable command, WEL=1.
Status Register is protected and can not be written to again
1 0 X Power Supply Lock-Down(1)
until the next Power-Down, Power-Up cycle.
11X
One Time Program
Status Register is permanently protected and can not be
written to.
NOTE:
Uniform Sector
1. When SRP1, SDRuP0a=l(1a, n0)d, a QPouwear-dDoSwne, rPioawlerF-Ulpacsyhcle will change SRP1, SRP0 to (0, 0) statGe. D25Q80B
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin a1re1 enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground)
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control
and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1
individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers
will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to
provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
SUS bit
The SUS bit is a read only bit in the status register (S15 ) that is set to 1 after executing an Erase/Program Suspend
(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down,
power-up cycle.
44 - 11
Rev.1.2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GD25Q80B.PDF ] | |
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