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Número de pieza | B154EW03-V1 | |
Descripción | WXGA Color TFT-LCD | |
Fabricantes | AUO | |
Logotipo | ||
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Product Specification
AU OPTRONICS CORPORATION
B154EW03 V1 (QD15TL08 Rev.02)
( ) Preliminary Specifications
(V ) Final Specifications
Module
Model Name
15.4” WXGA Color TFT-LCD
B154EW03 V1 (QD15TL08 REV.02)
Customer
Date
Checked &
Approved by
Note: This Specification is subject to
change without notice.
Approved by
Date
Beyond Yang
4/27/2007
Prepared by
Marcus Yen
4/27/2007
MDBU Marketing Division /
AU Optronics corporation
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3&6. 2CIG
4. Input Terminals
4-1. TFT-LCD panel driving
CN1 (1 channel, LVDS signals – NSC/Ti standard and +3.3V DC power supply)
Using connector: FI-XB30SL-HF10 (JAE) / equivalent
Interface Cable Pin Assignments
PIN NO . SYMBOL
FUNCTION
1 VSS
Ground
2 VDD
Power Supply, 3.3 V (typical)
3 VDD
Power Supply, 3.3 V (typical)
4
V EEDID
DDC 3.3V power
5 NC
Reserved for supplier test point
6
Clk EEDID
DDC Clock
7 DATA EEDID DDC Data
8 Rin0-
- LVDS differential data input (R0-R5, G0) (odd pixels)
9 Rin0+
+ LVDS differential data input (R0-R5, G0) (odd pixels)
10 VSS
Ground
11 Rin1-
- LVDS differential data input (G1-G5, B0-B1) (odd pixels)
12 Rin1+
+ LVDS differential data input (G1-G5, B0-B1) (odd pixels)
13 VSS
Ground
14 Rin2-
- LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
15 Rin2+
+ LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
16 VSS
Ground
17 ClkIN-
- LVDS differential clock input (odd pixels)
18 ClkIN+
+ LVDS differential clock input (odd pixels)
19 VSS
Ground
20 NC
No connect
21 NC
No connect
22 VSS
Ground
23 NC
No connect
24 NC
No connect
25 VSS
Ground
26 NC
No connect
27 NC
No connect
28 VSS
Ground
29 NC
No connect
30 NC
No connect
ޣNote 1ޤRelation between LVDS signals and actual data shows below section (4-2).
ޣNote 2ޤThe shielding case is connected with signal GND.
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7. Timing characteristics of LCD module input signals
7-1. Timing characteristics
(This is specified at digital outputs of LVDS driver.)
Data
ENAB
Sync
3&6. 2CIG
ዞ
ዟዠ
ዡ
ዝ
ዢ
ዄ Vertical ዅ
Itemዄsymbolዅ
Vsync cycle (TVA)
Blanking period(TVB)
Sync pulse width (TVC)
Back porch (TVD)
Sync pulse width + Back
porch (TVC+TVD)
Active display area (TVE)
Front porch (TVF)
Min.
ዉ
808
8
2
5
7
800
1
Typ.
16.667
816
16
4
8
12
800
4
Max.
ዉ
850
ዉ
35
ዉ
800
ዉ
Unit Remark
ms Negative
line
line
line
line
line
line
line
( Horizontal )
Itemዄsymbolዅ
Min.
Typ.
Max. Unit Remark
Hsync cycle (THA)
Blanking period (THB)
Sync pulse width (THC)
Back porch (THD)
Sync pulse width + Back
porch (THC +THD)
Active display area (THE)
Front porch (THF)
ዄClock ዅ
ዉ
1380
100
16
68
84
1280
16
20.44
1408
128
32
75
107
1280
21
ዉ
1428
ዉ
ዉ
ዉ
Ǵs
clock
clock
clock
clock
clock
Negative
1280
ዉ
clock
clock
Item
Min.
Typ.
Max. Unit Remark
Frequency
67.0 68.9
72 MHz ޣNote1ޤ
Note) In case of lower frequency, the deterioration of display quality, flicker etc., may be
occurred.
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11 Page |
Páginas | Total 25 Páginas | |
PDF Descargar | [ Datasheet B154EW03-V1.PDF ] |
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