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STMIPID02 반도체 회로 부품 판매점

Dual mode MIPI CSI-2 / SMIA CCP2 de-serializer



STMicroelectronics 로고
STMicroelectronics
STMIPID02 데이터시트, 핀배열, 회로
STMIPID02
Dual mode MIPI CSI-2 / SMIA CCP2 de-serializer
Features
Dual mode camera de-serializer
MIPI CSI-2 receivers (Rev.0.9 compliant)
– Two camera interfaces support
– One 1.6Gbps dual data lane receiver for
main camera with selectable 1/2 lane
operation
– One 800Mbps single data lane receiver for
second camera
– Each MIPI D-PHY interface with a 400MHz
DDR clock lane
– MIPI D-PHY Pass through mode
SMIA CCP2 receivers
– Two camera interfaces support
– 650Mbps class 2 receivers with selectable
data/clock and data/strobe operation
Support for MIPI CSI-2 and SMIA CCP2
RAW6, RAW7, RAW8 (Generic), RAW10 and
RAW12 Raw Bayer format data unpacking
Support for YUV, RGB and JPEG formats
Support for SMIA 8-10, 7-10, 6-10, 8-12, 7-12
& 6-12 DPCM/PCM decompression options
1V8, 200MHz,12-bit parallel output interface
HSYNC, VSYNC and continuous PCLK output
data qualification signal
Tristate-able output for dual camera systems
Error interrupt output (D-PHY and protocol)
MIPI CSI-2 short packet interrupt output
2-wires 100/400 kHz control interface
(I2C compatible slave) to configure D-PHY
timeouts and pixel data
unpacking/decompression options
Integrated power-on-reset cell
Digital power supply: 1.7V to 1.9V
Integrated 1.2V regulator for D-PHY and core
logic
VFBGA 49pin 3.0mm x 3.0mm x1.0mm F7x7
0.4mm pitch, 0.25mm ball package
Lead-free RoHS compliant product
Description
The STMIPID02 is a dual mode MIPI CSI-2 /
SMIA CCP2 de-serializer targeted at mobile
camera phone applications. Manufactured using
ST 65nm process, it integrates two MIPI CSI-2 /
SMIA CCP2 receivers. The STMIPID02 can then
support the main and the second cameras of a
mobile camera phone.
One of the two MIPI CSI-2 receivers is a dual lane
receiver allowing to connect high resolution / high
frame rate cameras.
The SMIA CCP2 compatible receivers share the
same input pins as the MIPI CSI-2 receivers.
STMIPID02’s 12-bit parallel output interface is
capable of outputting de-serialized pixel data at
rates up to 200MHz.
Pass through mode allows STMIPID02 to be used
as a standalone MIPI D-PHY physical layer
device.
With this device an host with a standard 8-bit, 10-
bit or 12-bit parallel input interface can be
connected to camera modules with either a MIPI
CSI-2 or a SMIA CCP2 low voltage, fully
differential bit-serial, low EMI interface.
An interrupt output for every MIPI CSI-2 short
packet.
Power management is simplified by the presence
of an integrated 1.2V regulator to supply the MIPI
D-PHY receiver and core logic.
STMIPID02 is fully configurable via an I2C
compatible slave control I/F.
March 2009
Draft Rev 0.7
For further information contact your local STMicroelectronics sales office.
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www.st.com
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STMIPID02 데이터시트, 핀배열, 회로
Block diagrams
1 Block diagrams
STMIPID02
Figure 1. Block diagram
Doubles
as CCP2
data &
clock/strobe
inputs
Data Lane 2
80-800Mbps
DATA1P2
DATA1N2
Clock Lane 2
40-400MHz
CLKP2
CLKN2
Data Lane 1.2
80-800Mbps
DATA2P1
DATA2N1
Doubles
as CCP2
data &
clock/strobe
inputs
Data Lane 1.1
80-800Mbps
DATA1P1
DATA1N1
Clock Lane 1
40-400MHz
CLKP1
CLKN1
Slave data lane module
Data lane
control
interface
logic
Slave clock lane module
Clock lane
control
interface
logic
MIPI D-PHY RX
Slave data lane module
Data lane
control
interface
logic
Slave data lane module
Data lane
control
interface
logic
Slave clock lane module
Clock lane
control
interface
logic
MIPI CSI-2 RX
Protocol
STMIPID02
SMIA CCP2 RX
Clock recovery &
de-serializer
XSDN
1.2V voltage
regulator (LDO)
Power
on
reset
JTAG
controller
Clock
manager
400kHz
I2C
slave
VDDOUT_LDO
1V8
ERROR
INT
1V8 12-bit parallel
interface @ 200MHz
D[11:0]
VSYNC
HSYNC
PCLK (up to 200MHz)
EXTCLK
6.0MHz - 27MHz
SDA
SCL
2/52 Draft Rev 0.7




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Dual mode MIPI CSI-2 / SMIA CCP2 de-serializer - STMicroelectronics