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P3041 반도체 회로 부품 판매점

QorIQ Integrated Processor



Freescale Semiconductor 로고
Freescale Semiconductor
P3041 데이터시트, 핀배열, 회로
Freescale Semiconductor
Data Sheet: Technical Data
P3041 QorIQ
Integrated Processor
Hardware Specifications
Document Number: P3041EC
Rev. 2, 02/2013
P3041
FC-PBGA–1295
37.5 mm x 37.5 mm
The P3041 QorIQ integrated processor utilizes four processor
cores built on Power Architecture® technology. The cores
include high-performance data path acceleration logic and
network and peripheral bus interfaces required for
networking, telecom/datacom, wireless infrastructure, and
aerospace applications.
This chip can be used for combined control, data path, and
application layer processing in routers, switches, base station
controllers, and general-purpose embedded computing. Its
high level of integration offers significant performance
benefits compared to multiple discrete devices while also
greatly simplifying board design.
The chip includes the following functions and features:
• Four e500mc Power Architecture cores, each with a
backside 128 KB L2 cache with ECC
– Three levels of instructions: User, supervisor, and
hypervisor
– Independent boot and reset
– Secure boot capability
• CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet end-points
• CoreNet platform cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os,
datapath accelerators, and high and low speed peripheral
interfaces
• One 10-Gigabit Ethernet (XAUI) controller
• Five 1-Gigabit Ethernet controllers
– SGMII interfaces
— 2.5 Gbps SGMII interfaces
– RGMII interfaces
• One 64-bit DDR3 SDRAM memory controller with ECC
• Multicore programmable interrupt controller
• Four I2C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller (eLBC)
• Four PCI Express 2.0 controllers/ports
• Two serial RapidIO® controllers/ports (sRIO port)
supporting version 1.3 with features from 2.1
• Two serial ATA (SATA 2.0) controllers
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interfaces (eSPI)
• 2× high-speed USB 2.0 controllers with integrated PHYs
© 2010–2013 Freescale Semiconductor, Inc. All rights reserved.


P3041 데이터시트, 핀배열, 회로
Table of Contents
1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3
1.1 1295 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . .3
1.2 Pinout List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .51
2.2 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3 Power-Down Requirements . . . . . . . . . . . . . . . . . . . . .58
2.4 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.5 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.6 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.7 Power-On Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.8 DDR3 and DDR3L SDRAM Controller . . . . . . . . . . . . .66
2.9 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
2.11 Ethernet: Datapath Three-Speed Ethernet (dTSEC),
Management Interface, IEEE Std 1588. . . . . . . . . . . . .78
2.12 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
2.13 Enhanced Local Bus Interface (eLBC) . . . . . . . . . . . . .87
2.14 Enhanced Secure Digital Host Controller (eSDHC) . . .91
2.15 Multicore Programmable Interrupt Controller (MPIC) and
Trust Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
2.16 JTAG Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
2.17 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.19 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 100
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 132
3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
3.2 Supply Power Default Setting . . . . . . . . . . . . . . . . . . 139
3.3 Power Supply Design . . . . . . . . . . . . . . . . . . . . . . . . 141
3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 143
3.5 SerDes Block Power Supply Decoupling
Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 143
3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 143
3.7 Recommended Thermal Model . . . . . . . . . . . . . . . . . 152
3.8 Thermal Management Information . . . . . . . . . . . . . . 153
4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 154
4.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 155
5 Security Fuse Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.1 Part Numbering Nomenclature . . . . . . . . . . . . . . . . . 156
6.2 Orderable Part Numbers Addressed by this Document157
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2
2 Freescale Semiconductor




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