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PDF WPCT301 Data sheet ( Hoja de datos )
| Número de pieza | WPCT301 | |
| Descripción | Trusted Platform Module (TPM) | |
| Fabricantes | Nuvoton | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de WPCT301 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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March 2011
Revision 1.40
WPCT301/NPCT501 Trusted Platform Module (TPM) Version
1.2 with I2C Interface
General Description
The Nuvoton WPCT301/NPCT501 family of single-chip
Trusted Platform Modules (TPM) is a third-generation Nu-
voton SafeKeeper device that implements the TCG ver-
sion 1.2 specification for PC-Client TPM with the addition of
a serial data interface.
The WPCT301/NPCT501 is designed to reduce system
power-up time and Trusted OS loading time. It provides a
complete platform security solution for a wide range of com-
puter systems.
Features
General
■ Complete, single-chip TPM solution
— No external parts required
■ Compatible with the Trusted Computing Group (TCG)
TPM 1.2 Main
■ Host Interface
— TPM 1.2 Interface (TIS) emulation
— Dedicated Interrupt signal
■ Secure General-Purpose I/O (GPIO)
— Up to three GPIO pins
— I/O pins individually configured as input or output
— Configurable internal pull-up resistors
— TCG 1.2-defined interface
— Dedicated Physical Presence (PP) pin with config-
urable pull-up or pull-down resistor
■ Tick Counter
Bus Interface
■ I2C Bus Interface
— I2C Slave
— Up to 400 KHz clock operation (NPCT501)
Clocking and Supply
■ On-Chip Clock Generator
■ Power Supply
— 3.3V supply operation
— Separate pins for main (VDD) and standby (VSB)
power supplies
— Low standby power consumption
Package
■ 28-pin Thin Shrink Small Outline Package (TSSOP28)
System Block Diagram
Host
© 2011 Nuvoton Technology Corporation
Physical
Presence
I2C Bus
WPCT301/
NPCT501
GPIO
www.nuvoton.com
1 page  
1.0 Signal/Pin Connection and Description (Continued)
1.3 SIGNAL/PIN DESCRIPTIONS
This section describes all signals of the WPCT301/NPCT501 device. The signals are organized by functional group.
1.3.1 Serial Interface
Signal
SDAT
SCLK
SINT
SRESET
Pin(s) I/O Buffer Type Power Well
Description
1 I/O INTS/OD4
2 I/O INTS/OD4
15 I/O INTS/OD8,
O4/8
16 I
INRST
VDD Serial Data In/Out. I2C data in/out.
VDD Serial Clock. I2C clock.
VDD Serial Communication Command Completion Interrupt.
Active low as long as there is data on the output data FIFO.
VDD Serial Reset. Host system reset used for the serial bus
(Hardware reset).
1.3.2 Inputs and Outputs
Signal
PP
GPIO4-2
Pin(s) I/O Buffer Type Power Well
Description
7I
15, 9, I/O
6
INTS
INTS/OD8,
O4/8
VDD Physical Presence Input. Indicates owner’s physical presence.
VDD General-Purpose I/O Port. General-Purpose I/O pins compatible
with the PC Client TPM 1.2 Specification.
1.3.3 Configuration Straps and Testing
Signal
TEST
SADD
XOR_OUT
Pin(s) I/O Buffer Type Power Well
Description
8I
INTS
9I
INTS
1O
O4/8
VDD Test Mode. Sampled at VDD Power-Up reset to force the device
pins into a XOR tree or TRI-STATE configuration, as follows:
– No pull-up resistor (default) - Normal device operation
– 4.7 K external pull-up resistor - Pins configured for Test mode.
VDD Serial Slave Address. Sampled at VDD Power-Up reset to select
the slave address, as follows:
- No pull-down resistor - AEh (write) and AFh (read)
- 10 Kexternal pull-down resistor - reserved for future
implementation. Do not use this option.
Test Mode Selection. Test mode (XOR tree or TRI-STATE) is
selected by the sampled state of the SADD pin during VDD
Power-Up reset. When SADD is sampled high, XOR Tree mode
is selected. When SADD is sampled low, TRI-STATE mode is
selected, floating all output pins.
VDD XOR Tree Output. This pin is the output of the XOR tree test logic.
1.3.4 Power and Ground
Signal
VSS
VDD
VSB
Pin(s) I/O Buffer Type Power Well
Description
4, 18,
25
19, 24
I
I
5I
GND
PWR
PWR
Ground. Ground connection for both core logic and I/O buffers,
for the Main, Standby and Battery power supplies.
Main 3.3V Power Supply. Powers the I/O buffers of the GPIO
ports and the serial interface.
Standby 3.3V Power Supply. Powers the on-chip core.
Revision 1.40
5 www.nuvoton.com
5 Page 
4.0 Device Specifications (Continued)
4.1.4 Power Consumption under Recommended Operating Conditions
Symbol
Parameter
Conditions1
Typ
IDD VDD Average Supply Current
VIL = 0.5V, VIH = 2.4V, No Load
5
ISB VSB Average Supply Current
VIL = 0.5V, VIH = 2.4V, No Load
20
ISBLP
VSB Quiescent Supply Current in
Idle Mode2
VIL = VSS, VIH = VSB, No Load
300
1. All parameters specified for 0C TA 70C; VDD and VSB = 3.3V 10% unless otherwise specified.
2. Device is not performing any operation; no Serial bus activity.
Max
10
50
700
Unit
mA
mA
A
Revision 1.40
11 www.nuvoton.com
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet WPCT301.PDF ] | |
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