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Supertex Inc |
Supertex inc.
VN0109
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
►► Free from secondary breakdown
►► Low power drive requirement
►► Ease of paralleling
►► Low CISS and fast switching speeds
►► Excellent thermal stability
►► Integral source-drain diode
►► High input impedance and high gain
Applications
►► Motor controls
►► Converters
►► Amplifiers
►► Switches
►► Power supply circuits
►► Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
General Description
This enhancement-mode (normally-off) transistor utilizes
a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors and the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Part Number
Package Option
VN0109N3-G
TO-92
VN0109N3-G P002
Packing
1000/Bag
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
90V 3.0Ω
IDSS
(min)
2.0A
VN0109N3-G P003
VN0109N3-G P005
TO-92
2000/Reel Pin Configuration
VN0109N3-G P013
VN0109N3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Absolute Maximum Ratings
SOURCE
DRAIN
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature
-55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
GATE
TO-92
Product Marking
SiVN YY = Year Sealed
0 1 0 9 WW = Week Sealed
YYWW
= “Green” Packaging
Typical Thermal Resistance
Package
θja
TO-92
132OC/W
Package may or may not include the following marks: Si or
TO-92
Doc.# DSFP-VN0109
C081913
Supertex inc.
www.supertex.com
Thermal Characteristics
Package
(continIDuous)†
TO-92
350mA
Notes:
† ID (continuous) is limited by max rated Tj .
ID
(pulsed)
2.0A
Power Dissipation
@TC = 25OC
1.0W
IDR†
350mA
VN0109
IDRM
2.0A
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
90 - - V VGS = 0V, ID = 1.0mA
VGS(th) Gate threshold voltage
0.8 - 2.4 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- -3.8 -5.5 mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage
- - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 1.0
VGS = 0V, VDS = Max Rating
-
-
100
µA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
0.5 1.0
2.0 2.5
-
-
A VGS = 5.0V, VDS = 25V
VGS = 10V, VDS = 25V
RDS(ON) Static drain-to-source on-state resistance
- 3.0 5.0
- 2.5 3.0
Ω VGS = 5.0V, ID = 250mA
VGS = 10V, ID = 1.0A
ΔRDS(ON) Change in RDS(ON) with temperature
- 0.70 1.0 %/OC VGS = 10V, ID = 1.0A
GFS Forward transductance
300 450
- mmho VDS = 25V, ID = 500mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 55 65
VGS = 0V,
- 20 25 pF VDS = 25V,
- 5.0 8.0
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- 3.0 5.0
- 5.0 8.0
VDD = 25V,
-
6.0 9.0
ns ID = 1.0A,
RGEN = 25Ω
- 5.0 8.0
VSD Diode forward voltage drop
- 1.2 1.8
V VGS = 0V, ISD = 1.0A
trr Reverse recovery time
- 400 -
ns VGS = 0V, ISD = 1.0A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
INPUT
0V
10%
t(ON)
90%
t(OFF)
td(ON)
tr
td(OFF)
tf
VDD
OUTPUT
0V
10%
90%
10%
90%
Pulse
Generator
RGEN
INPUT
VDD
RL
OUTPUT
D.U.T.
Doc.# DSFP-VN0109
C081913
Supertex inc.
2 www.supertex.com
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