파트넘버.co.kr VP0300 데이터시트 PDF


VP0300 반도체 회로 부품 판매점

P-Channel Enhancement-Mode Vertical DMOS FETs



Supertex 로고
Supertex
VP0300 데이터시트, 핀배열, 회로
VP0300
P-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BVDSS /
BVDGS
-30V
RDS(ON)
(max)
2.5
ID(ON)
(min)
-1.5A
Order Number / Package
TO-92
VP0300L
Features
s Free from secondary breakdown
s Low power drive requirement
s Ease of paralleling
s Low CISS and fast switching speeds
s Excellent thermal stability
s Integral Source-Drain diode
s High input impedance and high gain
s Complementary N- and P-channel devices
Applications
s Motor controls
s Converters
s Amplifiers
s Switches
s Power supply circuits
s Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces devices with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inher-
ent in MOS devices. Characteristic of all MOS structures, these
devices are free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where high breakdown
voltage, high input impedance, low input capacitance, and fast
switching speeds are desired.
9
Package Options
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
* Distance of 1.6 mm from case for 10 seconds.
BVDSS
BVDGS
± 20V
-55°C to +150°C
300°C
7-227
SGD
TO-92
Note: See Package Outline section for dimensions.


VP0300 데이터시트, 핀배열, 회로
Thermal Characteristics
Package
ID (continuous)*
ID (pulsed)
TO-92
-0.32A
* ID (continuous) is limited by max rated Tj.
-0.87A
Power Dissipation
TC = 25°C
1.0W
θja
°C/W
170
θjc
°C/W
125
VP0300
Electrical Characteristics (@ 25°C unless otherwise specified)
Symbol
BVDSS
VGS(th)
IGSS
IDSS
Parameter
Drain-to-Source Breakdown Voltage
Gate Threshold Voltage
Gate Body Leakage
Zero Gate Voltage Drain Current
Min Typ Max
-30
-1.0 -1.8 -4.5
-100
-10
-500
Unit
V
V
nA
µA
ID(ON)
ON-State Drain Current
-1.5 -1.7
RDS(ON) Static Drain-to-SourceON-State Resistance
2.5
GFS Forward Transconductance
200
CISS Input Capacitance
150
COSS
Common Source Output Capacitance
120
CRSS
Reverse Transfer Capacitance
60
t(ON) Turn-ON Time
30
t(OFF)
Turn-OFF Time
30
VSD Diode Forward Voltage Drop
-1.2
Notes
1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
A
m
pF
ns
V
Conditions
VGS= 0V, ID =-10µA
VGS = VDS, ID = -1mA
VGS = ±30V, VDS = 0V
VGS = 0V, VDS = -25V
VGS = 0V, VDS = -25V
TA = 125°C
VGS = -12V, VDS = -10V
VGS = -12V, ID = -1A
VDS = -10V, ID = -0.5A
VGS = 0V, VDS = -15V
f = 1MHz
VDD = -25V, ID = -1A
RGEN = 25
VGS = 0V, ISD = -1.5A
Switching Waveforms and Test Circuit
0V
INPUT
-10V
0V
OUTPUT
VDD
10%
t(ON)
td(ON)
tr
90%
t(OFF)
td(OFF)
tF
90%
90%
10%
10%
PULSE
GENERATOR
Rgen
INPUT
D.U.T.
OUTPUT
RL
VDD
7-228




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