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PDF H9CKNNN8GTMPLR Data sheet ( Hoja de datos )
| Número de pieza | H9CKNNN8GTMPLR | |
| Descripción | 8Gb LPDDR3 | |
| Fabricantes | Hynix | |
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168ball FBGA Specification
8Gb LPDDR3 (x32)
This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 1.1 / Oct. 2013
1
1 page  
H9CKNNN8GTMPLR
LPDDR3-S8B 8Gb(x32)
ORDERING INFORMATION
Part Number
Memory
Combination
Operation
Voltage
H9CKNNN8GTMPLR-NTH LPDDR3 S8B 1.8V/1.2/1.2/1.2
H9CKNNN8GTMPLR-NUH LPDDR3 S8B 1.8V/1.2/1.2/1.2
Density
8Gb(x32)
8Gb(x32)
Speed
Package
DDR3 1600
168Ball FBGA
(Lead & Halogen Free)
DDR3 1866
168Ball FBGA
(Lead & Halogen Free)
H9CKNNN8GTMPLR-N*H
SK Hynix Memory
MCP/PoP
Product Mode :
PoP LPDDR3 only
Density, Stack, Block Size
& Page Buffer for NVM1) :
None
Voltage & I/O for NVM :
None
Density, Stack, CH & CS for DRAM :
8Gb, SDP
Voltage, I/O & Option for DRAM :
1.2v/1.2, x32, LPDDR3
Temperature :
Mobile (-30~105’C)
DRAM Speed
NAND Speed : none
Package Material :
Lead & Halogen Free
Package Type :
FBGA 168 Ball 12x12
Generation : 1st
Rev 1.1 / Oct. 2013
5
5 Page 
H9CKNNN8GTMPLR
LPDDR3-S8B 8Gb(x32)
Functional Description
LPDDR3-SDRAM is a high-speed synchronous DRAM device internally configured as an 8-bank memory.
These devices contain the following number of bits:
4 Gb has 4,294,967,296 bits
8 Gb has 8,589,934,592 bits
16 Gb has 17,179,869,184 bits
32 Gb has 34,359,738,368 bits
LPDDR3 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input
pins in the system. The 10-bit CA bus contains command, address, and bank information. Each command uses one clock
cycle, during which command information is transferred on both the positive and negative edge of the clock.
These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The double data
rate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits per DQ
every clock cycle at the I/O pins. A single read or write access for the LPDDR3 SDRAM effectively consists of a single
8n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half-clock-
cycle data transfers at the I/O pins.
Read and write accesses to the LPDDR3 SDRAMs are burst oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activate
command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the
Activate command are used to select the row and the bank to be accessed. The address bits registered coincident with
the Read or Write command are used to select the bank and the starting column location for the burst access.
Prior to normal operation, the LPDDR3 SDRAM must be initialized. The following section provides detailed information
covering device initialization, register definition, command description and device operation.
LPDDR3 SDRAM Addressing
Density
Number of Banks
Bank Addresses
tREFI(us)
x16
Row Addresses
Column Addresses
x32
Row Addresses
Column Addresses
4Gb
8
BA0 - BA2
3.9
R0 - R13
C0 - C10
R0 - R13
C0 - C9
8Gb
8
BA0 - BA2
3.9
R0 - R14
C0 - C10
R0 - R14
C0 - C9
Note:
1. The least-significant column address C0, C1 is not transmitted on the CA bus, and is implied to be zero.
2. tREFI values for all bank refresh is Tc = -30 ~ 85 °C, Tc means Operating Case Temperature.
3. Row and Column Address values on the CA bus which are not used are “don’t care”.
16Gb
8
BA0 - BA2
3.9
R0 - R14
C0 - C11
R0 - R14
C0 - C10
Rev 1.1 / Oct. 2013
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet H9CKNNN8GTMPLR.PDF ] | |
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