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PDF A25L16P Data sheet ( Hoja de datos )
| Número de pieza | A25L16P | |
| Descripción | Serial Flash Memory | |
| Fabricantes | AMIC Technology | |
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A25L16P Series
Preliminary
16 Mbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
Document Title
16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
History
Initial issue
Change part no. from A25L160P to A25L16P
Change the frequency to 70 MHz
Add the Fast Read Dual Input-Output Mode
Add QFN 8L (5 x 6mm) package type
Top or bottom boot block configuration available
Change the frequency to 85 MHz
Remove the REMS mode
Correct the A25LPT memory organization of Table 2-1
Reduce the options of protected area size to all sectors
protected and all sectors unprotected
Modify the ICC1 and ICC3 of Table 10
Modify the tW and tBE of Table 11
Add transient voltage (<20ns) on any pin to ground potential spec.
Issue Date
March 10, 2006
March 23, 2006
March 27, 2006
April 20, 2006
December 5, 2006
February 6, 2007
April 24, 2007
Remark
Preliminary
PRELIMINARY (April, 2007, Version 0.6)
AMIC Technology Corp.
http://www.Datasheet4U.com
1 page  
Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)
SDO
SDI
SCK
Bus Master
(ST6, ST7, ST9,
ST10, Other)
CS3 CS2 CS1
CQD
SPI Memory
Device
S W HOLD
CQD
SPI Memory
Device
S W HOLD
A25L16P Series
CQD
SPI Memory
Device
S W HOLD
Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL CPHA
00
C
11
C
DIO
DO
MSB
MSB
PRELIMINARY (April, 2007, Version 0.6)
4
AMIC Technology Corp.
5 Page 
Write Enable (WREN)
The W rite Enable (W REN) instructio n (F igure 4.) sets the
Write Enable Latch (WEL) bit.
The Write Enable Latch (W EL) bit must be set prior to ever y
Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.
A25L16P Series
The W rite Ena ble (W REN) in struction is ent ered b y driv ing
Chip Select ( S ) Low, sending the instruction code, and then
driving Chip Select ( S ) High.
Figure 4. Write Enable (WREN) Instruction Sequence
S
01 23 45 67
C
Instruction
DIO
High Impedance
DO
Write Disable (WRDI)
The Write Disable (W RDI) i nstruction (F igure 5.) resets the
Write Enable Latch (WEL) bit.
The W rite Disable (W RDI) i nstruction is e ntered b y driving
Chip Select ( S ) Low, sending the inst ruction code, and then
driving Chip The Write Enable Latch (WEL) bit is reset unde r
the following conditions:
﹣ Power-up
﹣ Write Disable (WRDI) instruction completion
﹣ Write Status Register (WRSR) instruction completion
﹣ Page Program (PP) instruction completion
﹣ Sector Erase (SE) instruction completion
﹣ Bulk Erase (BE) instruction completion
Figure 5. Write Disable (WRDI) Instruction Sequence
S
01 23 45 67
C
Instruction
DIO
High Impedance
DO
PRELIMINARY (April, 2007, Version 0.6)
10
AMIC Technology Corp.
11 Page | ||
| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet A25L16P.PDF ] | |
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