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SSM3J334R 반도체 회로 부품 판매점

Power Management Switch Applications



Toshiba Semiconductor 로고
Toshiba Semiconductor
SSM3J334R 데이터시트, 핀배열, 회로
SSM3J334R
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSVI)
SSM3J334R
Power Management Switch Applications
Lo w ON-resistance: RDS(ON) = 71 m(max) (@VGS = -10 V)
R DS(ON) = 105 m(max) (@VGS = -4.5 V)
R DS(ON) = 136 m(max) (@VGS = -4.0 V)
0.05 M A
0.42+-00..0058
3
Unit: mm
0.17
+0.08
-0.07
Absolute Maximum Ratings (Ta = 25°C)
Characteristic S
Drain-Source voltage
Gate-Source voltage
Drain current
DC I
Pulse
Power dissipation
Channel temperature
Storage temperature range
ymbol
VDSS
VGSS
D (Note 1)
IDP (Note 1,2)
PD (Note 3)
t < 10s
Tch
Tstg
Rating
-30
± 20
-4
-16
1
2
150
55 to 150
Unit
V
V
A
W
°C
°C
1
0.95
2
0.95
2.9±0.2
A
SOT-23F
1: Gate
2: Source
3: Drain
Note: Using co ntinuously under heavy loads (e.g. the application of high
JEDEC
temperature/current/voltage and the si gnificant ch ange in
temperature, e tc.) ma y ca use th is product to decr ease in th e
JEITA
reliability si gnificantly eve n if the oper ating co nditions (i.e.
TOSHIBA
2-3Z1A
operating te mperature/current/voltage, e tc.) are
absolute maximum ratings.
within th e
Weight: 11 mg (typ.)
Please desig n the appropri ate relia bility upon revie wing the
Toshiba Semic onductor Reli ability Handbook (“Handli ng Precautions”/“Derating Conce pt and Method s”) and
individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: The channel temperature should not exceed 150°C during use.
Note 2: PW 1ms, Duty 1
Note 3: Mounted on a FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
Marking
3
Equivalent Circuit (Top View)
3
KFL
12
12
Start of commercial production
2010-08
1 2014-03-01
http://www.Datasheet4U.com


SSM3J334R 데이터시트, 핀배열, 회로
SSM3J334R
Electrical Characteristics (Ta = 25°C)
Characteristic S
ymbol
Test Conditions Min
Typ. Max Unit
Drain-Source breakdown voltage
V (BR) DSS ID = -10 mA, VGS = 0 V
V (BR) DSX ID = -10 mA, VGS = 10 V
.(Note 5)
-30
-21
V
V
Drain cut-off current
IDSS
VDS = -30 V, VGS = 0 V
⎯ ⎯ -1
μA
Gate leakage current
IGSS VGS = ±16 V, VDS = 0 V
⎯ ⎯ ±10 μA
Gate threshold voltage
Vth VDS = -10 V, ID = -100 μA -0.8
-2.0
V
Forward transfer admittance
YfsVDS = -10 V, ID = -1.0 A
(Note 4) 2.3 4.6 S
ID = -3.0 A, VGS = -10 V
(Note 4) 54 71
Drain–source ON-resistance
RDS (ON) ID = -2.0 A, VGS = -4.5 V
(Note 4)
80 105 mΩ
ID = -1.0 A, VGS = -4.0 V
(Note 4)
89 136
Input capacitance
Output capacitance
Reverse transfer capacitance
Ciss
Coss
Crss
VDS = -15 V, VGS = 0 V
f = 1 MHz
280
55
40
pF
Switching time
Turn-on time
Turn-off time
ton VDD = -15 V, ID = -1.0 A
toff VGS = 0 to -4.5 V, RG = 10 Ω
13
ns
22
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Qg
Qgs1
Qgd
VDD = -15 V, ID = -4.0 A,
VGS = -10 V
5.9
0.8
1.2
nC
Drain-Source forward voltage
VDSF ID = 4.0 A, VGS = 0 V
(Note 4)
0.9 1.2
V
Note4: Pulse test
Note5: If a for ward bi as is appli ed bet ween gate and sourc e, this devic e enters V (BR)DSX mode. Note that the
drain-source breakdown voltage is lowered in this mode.
Switching Time Test Circuit
(a) Test Circuit
0 IN
4.5V
10 μs
VDD = -15 V
RG = 10 Ω
Duty 1%
VIN: tr, tf < 5 ns
Common Source
Ta = 25°C
OUT
RL
VDD
(b) VIN
0V
4.5 V
(c) VOUT VDS (ON)
VDD
90%
10%
90%
10%
tr
ton toff
tf
Notice on Usage
Let Vth be the voltage applied between gate and sour ce that causes the drain current (ID) to be l ow (-100μA for the
SSM3J334R). Then, for norma l switching operation, VGS(on) must be h igher than V th, and VGS(off) must be lo wer than
Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on).
Take this into consideration when using the device.
Handling Precaution
When han dling indivi dual de vices that are not yet mount ed on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance Rth (ch-a) and power dissipation PD vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration
2 2014-03-01




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Power Management Switch Applications - Toshiba Semiconductor