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2128VL 반도체 회로 부품 판매점

2.5VIn-SystemProgrammableSuperFASTHighDensityPLD



LatticeSemiconductor 로고
LatticeSemiconductor
2128VL 데이터시트, 핀배열, 회로
ispLSI® 2128VL
2.5V In-System Programmable
SuperFAST™ High Density PLD
Features
Functional Block Diagram*
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2128V and 2128VE Devices
• 2.5V LOW VOLTAGE 2128 ARCHITECTURE
— Interfaces with Standard 3.3V Devices (Inputs and
I/Os are 3.3V Tolerant)
— 125 mA Typical Active Current
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 150 MHz Maximum Operating Frequency
tpd = 6.0 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Output Routing Pool (ORP)
D7 D6 D5 D4
Output Routing Pool (ORP)
D3 D2 D1 D0
A0 C7
A1 C6
A2
DQ
C5
A3 C4
DQ
Logic
A4
Array
DQ
GLB
C3
A5 C2
DQ
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3
Output Routing Pool (ORP)
B4 B5 B6 B7
Output Routing Pool (ORP)
*128 I/O version shown
0139A/2128VL
Description
The ispLSI 2128VL is a High Density Programmable
Logic Device available in 128 and 64 I/O-pin versions.
The device contains 128 Registers, eight Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2128VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2128VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2128VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2128vL_02
1


2128VL 데이터시트, 핀배열, 회로
Specifications ispLSI 2128VL
Functional Block Diagram
Figure 1. ispLSI 2128VL Functional Block Diagram (128-I/O and 64-I/O Versions)
RESET
GOE 0
GOE 1
Megablock
Generic Logic
Blocks (GLBs)
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
D7 D6 D5 D4 D3 D2 D1 D0
C7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
TDI/IN 0
TMS/IN 1
BSCAN
A0
A1
A2
Global
Routing
A3
Pool
(GRP)
A4
A5
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
C6
C5
C4
C3
C2
C1
C0
IN 5
IN 4
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
0139B/2128VL
RESET
GOE 0
GOE 1
Megablock
Generic Logic
Blocks (GLBs)
I/O 0
I/O 1
I/O 2
I/O 3
A0
Input Bus
Output Routing Pool (ORP)
D7 D6 D5 D4 D3 D2 D1 D0
C7
C6
IN 5*
IN 4*
I/O 47
I/O 46
I/O 45
I/O 44
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
A1
A2
A3
A4
A5
Global
Routing
Pool
(GRP)
I/O 43
C5 I/O 42
I/O 41
I/O 40
C4
C3
I/O 39
I/O 38
C2 I/O 37
I/O 36
C1
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
C0
I/O 35
I/O 34
I/O 33
I/O 32
BSCAN
Output Routing Pool (ORP)
Input Bus
0139B/2128VL.64IO
*Not available on 84-PLCC Device
The 128-I/O 2128VL contains 128 I/O cells, while the 64-
I/O version contains 64 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control, and the output
drivers can source 4mA or sink 8mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 3.3V signal levels to support
mixed-voltage systems.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
the two or one ORPs. Each ispLSI 2128VL device con-
tains four Megablocks.
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2128VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
2




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