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PDF PZ5032 Data sheet ( Hoja de datos )
| Número de pieza | PZ5032 | |
| Descripción | 32 macrocell CPLD | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
PZ5032
32 macrocell CPLD
Product specification
IC27 Data Handbook
Philips
Semiconductors
1997 Feb 20
Free Datasheet http://www.Datasheet4U.com
1 page  
Philips Semiconductors
32 macrocell CPLD
Product specification
PZ5032
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the
CoolRunner™ family. The macrocell consists of a flip-flop that can be
configured as either a D or T type. A D-type flip-flop is generally
more useful for implementing state machines and data buffering. A
T-type flip-flop is generally more useful in implementing counters. All
CoolRunner™ family members provide both synchronous and
asynchronous clocking and provide the ability to clock off either the
falling or rising edges of these clocks. These devices are designed
such that the skew between the rising and falling edges of a clock
are minimized for clocking integrity. There are 2 clocks (CLK0 and
CLK1) available on the PZ5032 device. Clock 0 (CLK0) is
designated as the “synchronous” clock and must be driven by an
external source. Clock 1 (CLK1) can either be used as a
synchronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation).
Two of the control terms (CT0 and CT1) are used to control the
Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature
for each macrocell can also be disabled. Note that the Power-on
Reset leaves all macrocells in the “zero” state when power is
properly applied. The other 4 control terms (CT2–CT5) can be used
to control the Output Enable of the macrocell’s output buffers. The
reason there are as many control terms dedicated for the Output
Enable of the macrocell is to insure that all CoolRunner™ devices
are PCI compliant. The macrocell’s output buffers can also be
always enabled or disabled. All CoolRunner™ devices also provide a
Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all
the outputs of the device. This pin is provided to support “In-Circuit
Testing” or “Bed-of-Nails Testing”.
There are two feedback paths to the ZIA: one from the macrocell,
and one from the I/O pin. The ZIA feedback path before the output
buffer is the macrocell feedback path, while the ZIA feedback path
after the output buffer is the I/O pin ZIA path. When the macrocell is
used as an output, the output buffer is enabled, and the macrocell
feedback path can be used to feedback the logic implemented in the
macrocell. When the I/O pin is used as an input, the output buffer
will be 3-Stated and the input signal will be fed into the ZIA via the
I/O feedback path, and the logic implemented in the buried
macrocell can be fed back to the ZIA via the macrocell feedback
path. It should be noted that unused inputs or I/Os should be
properly terminated.
TO ZIA
CLK0
CLK0
CLK1
CLK1
D/T Q
INIT
(P or R)
GTS
CT0
CT1
GND
CT2
CT3
CT4
CT5
VCC
GND
Figure 3. PZ5032 Macrocell Architecture
GND
SP00440
1997 Feb 20
75
Free Datasheet http://www.Datasheet4U.com
5 Page 
Philips Semiconductors
32 macrocell CPLD
Product specification
PZ5032
PIN DESCRIPTIONS
PZ5032 – 44-Pin Plastic Leaded Chip Carrier
6
7
1 40
39
PLCC
17
18
29
28
Pin Function
1 IN1
2 IN3
3 VDD
4 I/O–A0–CK1
5 I/O–A1
6 I/O–A2
7 I/O–A3
8 I/O–A4
9 I/O–A5
10 GND
11 I/O–A6
12 I/O–A7
13 I/O–A8
14 I/O–A9
15 VDD
Pin Function
16 I/O–A10
17 I/O–A11
18 I/O–A12
19 I/O–A13
20 I/O–A14
21 I/O–A15
22 GND
23 VDD
24 I/O–B15
25 I/O–B14
26 I/O–B13
27 I/O–B12
28 I/O–B11
29 I/O–B10
30 GND
Pin Function
31 I/O–B9
32 I/O–B8
33 I/O–B7
34 I/O–B6
35 VDD
36 I/O–B5
37 I/O–B4
38 I/O–B3
39 I/O–B2
40 I/O–B1
41 I/O–B0
42 GND
43 IN0–CK0
44 IN2–gtsn
SP00420
PZ5032 – 44-Pin Thin Quad Flat Package
44
1
34
33
TQFP
Pin Function
1 I/O–A3
2 I/O–A4
3 I/O–A5
4 GND
5 I/O–A6
6 I/O–A7
7 I/O–A8
8 I/O–A9
9 VDD
10 I/O–A10
11 I/O–A11
12 I/O–A12
13 I/O–A13
14 I/O–A14
15 I/O–A15
11
12
23
22
Pin Function
16 GND
17 VDD
18 I/O–B15
19 I/O–B14
20 I/O–B13
21 I/O–B12
22 I/O–B11
23 I/O–B10
24 GND
25 I/O–B9
26 I/O–B8
27 I/O–B7
28 I/O–B6
29 VDD
30 I/O–B5
Pin Function
31 I/O–B4
32 I/O–B3
33 I/O–B2
34 I/O–B1
35 I/O–B0
36 GND
37 IN0/CK0
38 IN2–gtsn
39 IN1
40 IN3
41 VDD
42 I/O–A0–CK1
43 I/O–A1
44 I/O–A2
SP00433
Package Thermal Characteristics
Philips Semiconductors uses the Temperature Sensitive Parameter
(TSP) method to test thermal resistance. This method meets
Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC
Package Databook. Thermal resistance varies slightly as a function
of input power. As input power increases, thermal resistance
changes approximately 5% for a 100% change in power.
Figure 7 is a derating curve for the change in ΘJA with airflow based
on wind tunnel measurements. It should be noted that the wind flow
dynamics are more complex and turbulent in actual applications
than in a wind tunnel. Also, the test boards used in the wind tunnel
contribute significantly to forced convection heat transfer, and may
not be similar to the actual circuit board, especially in size.
Package
44-pin PLCC
44-pin TQFP
ΘJA
49.8°C/W
66.3°C/W
PERCENTAGE
REDUCTION IN
ΘJA (%)
0
10
20
30
40
50
0
PLCC/
QFP
1 2 34
AIR FLOW (m/s)
5
SP00419A
Figure 7. Average Effect of Airflow on ΘJA
1997 Feb 20
81
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet PZ5032.PDF ] | |
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