PDF MX25L25735E Data sheet ( Hoja de datos )

Número de pieza	MX25L25735E
Descripción	FLASH MEMORY
Fabricantes	MACRONIX
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No Preview Available ! MX25L25735E MX25L25735E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1586 REV. 1.2, FEB. 10, 2012 1 http://www.Datasheet4U.com 1 page MX25L25735E 256M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four I/O mode) structure • 8192 Equal Sectors with 4K bytes each - Any Sector can be erased individually • 1024 Equal Blocks with 32K bytes each - Any Block can be erased individually • 512 Equal Blocks with 64K bytes each - Any Block can be erased individually • Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • 4-bytes address interface • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance VCC = 2.7~3.6V - Normal read - 50MHz - Fast read - 1 I/O: 80MHz with 8 dummy cycles - 2 I/O: 70MHz with 4 dummy cycles - 4 I/O: 70MHz with 6 dummy cycles - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Continuously Program mode (automatically increase address under word program mode) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.5s(typ.) /block (32K-byte per block); 0.7s(typ.) /block (64K-byte per block); 160s(typ.) /chip • Low Power Consumption - Low active read current: 45mA(max.) at 80MHz, 40mA(max.) at 70MHz and 30mA(max.) at 50MHz - Low active programming current: 25mA (max.) - Low active erase current: 25mA (max.) - Standby current: 200uA (max.) - Deep power down current: 80uA (max.) • Typical 100,000 erase/program cycles SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - BP0-BP3 block group protect - Flexible individual block protect when OTP WPSEL=1 P/N: PM1586 REV. 1.2, FEB. 10, 2012 5 http://www.Datasheet4U.com 5 Page MX25L25735E Table 2. Protected Area Sizes Status bit Protection Area BP3 BP2 BP1 BP0 256Mb 0 0 0 0 0 (none) 0 0 0 1 1 (2 blocks, block 510th-511th) 0 0 1 0 2 (4 blocks, block 508th-511th) 0 0 1 1 3 (8 blocks, block 504th-511th) 0 1 0 0 4 (16 blocks, block 496th-511th) 0 1 0 1 5 (32 blocks, block 480th-511th) 0 1 1 0 6 (64 blocks, block 448nd-511th) 0 1 1 1 7 (128 blocks, block 384th-511th) 1 0 0 0 8 (256 blocks, block 256th-511th) 1 0 0 1 9 (512 blocks, all) 1 0 1 0 10 (512 blocks, all) 1 0 1 1 11 (512 blocks, all) 1 1 0 0 12 (512 blocks, all) 1 1 0 1 13 (512 blocks, all) 1 1 1 0 14 (512 blocks, all) 1 1 1 1 15 (512 blocks, all) Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de- vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se- cured OTP Definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu- rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se- cured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range xxx000~xxx00F xxx010~xxx1FF Size 128-bit 3968-bit Standard Factory Lock ESN (electrical serial number) N/A Customer Lock Determined by customer P/N: PM1586 11 REV. 1.2, FEB. 10, 2012 http://www.Datasheet4U.com 11 Page

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