J649 반도체 회로 부품 판매점
P-Channel MOSFET ( Transistor ) - 2SJ649
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 NEC |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SJ649
SWITCHING
P-CHANNEL POWER MOS FET
DESCRIPTION
The 2SJ649 is P-channel MOS Field Effect Transistor designed
for solenoid, motor and lamp driver.
ORDERING INFORMATION
PART NUMBER
PACKAGE
2SJ649
Isolated TO-220
FEATURES
• Low on-state resistance:
RDS(on)1 = 48 mΩ MAX. (VGS = –10 V, ID = –10 A)
RDS(on)2 = 75 mΩ MAX. (VGS = –4.0 V, ID = –10 A)
• Low input capacitance:
Ciss = 1900 pF TYP. (VDS = –10 V, VGS = 0 V)
• Built-in gate protection diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
Total Power Dissipation (TC = 25°C)
VDSS
VGSS
ID(DC)
ID(pulse)
PT
–60
m 20
m 20
m 70
25
V
V
A
A
W
Total Power Dissipation (TA = 25°C)
PT 2.0 W
Channel Temperature
Tch 150 °C
Storage Temperature
Single Avalanche Current Note2
Single Avalanche Energy Note2
Tstg –55 to +150 °C
IAS –20 A
EAS 40 mJ
(Isolated TO-220)
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, VDD = –30 V, RG = 25 Ω, VGS = –20 ¡ 0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D16332EJ1V0DS00 (1st edition)
Date Published May 2003 NS CP(K)
Printed in Japan
2002
Free Datasheet http://www.datasheet4u.net/
2SJ649
ELECTRICAL CHARACTERISTICS (TA = 25°C)
Characteristics
Symbol
Test Condtions
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
IDSS
IGSS
VGS(off)
| yfs |
RDS(on)1
VDS = –60 V, VGS = 0 V
VGS = m 20 V, VDS = 0 V
VDS = –10 V, ID = –1 mA
VDS = –10 V, ID = –10 A
VGS = –10 V, ID = –10 A
RDS(on)2 VGS = –4.0 V, ID = –10 A
Input Capacitance
Ciss VDS = –10 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
VDD = –30 V, ID = –10 A
Rise Time
tr VGS = –10 V
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG VDD = –48 V
Gate to Source Charge
QGS VGS = –10 V
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
ID = –20 A
IF = 20 A, VGS = 0 V
Reverse Recovery Time
trr IF = 20 A, VGS = 0 V
Reverse Recovery Charge
Qrr
Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2%
di/dt = 100 A/µs
MIN. TYP. MAX.
–10
m 10
–1.5 –2.0 –2.5
10 20
38 48
47 75
1900
350
140
10
10
73
17
38
7
10
0.95
49
100
Unit
µA
µA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG
VGS = –20 → 0 V
50 Ω
L
VDD
− IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS (−)
0
τ
τ = 1 µs
Duty Cycle ≤ 1%
RL
VDD
VGS (−)
VGS
Wave Form
0 10%
VDS (−)
90%
VDS
VDS
0
Wave Form
td(on)
90%
VGS
10% 10%
90%
tr td(off) tf
ton toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet D16332EJ1V0DS
Free Datasheet http://www.datasheet4u.net/
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