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RK3188 반도체 회로 부품 판매점

Technical Reference Manual



Rockchip 로고
Rockchip
RK3188 데이터시트, 핀배열, 회로
RK3188Technical Reference ManualRev 1.2
Chapter 1 Introduction
RK3188 is a low power, high performance processor for mobile phones, personal
mobile internet device and other digital multimedia applications, and integrates
quad-core Cortex-A9 with separately NEONand FPU coprocessor.
Many embedded powerful hardware engines provide optimized performance for
high-end application. RK3188 supports almost full-format video decoder by
1080p@60fps, also support H.264/MVC/VP8 encoder by 1080p@30fps,
high-quality JPEG encoder/decoder, special image preprocessor and
postprocessor.
Embedded 3D GPU makes RK3188 completely compatible with OpenGL ES2.0
and 1.1, OpenVG 1.1. Special 2D hardware engine with MMU will maximize
display performance and provide very smoothly operation.
RK3188 has high-performance external memory
interface(DDR3/LPDDR2/LVDDR3) capable of sustaining demanding memory
bandwidths, also provides a complete set of peripheral interface to support very
flexible applications as follows :
z 2 banks, 8bits/16bits Nor Flash/SRAM interface
z 4 banks, 8bits/16bits async Nand Flash,LBA Nand Flash and 8bits sync
ONFI Nand Flash, allup to 60bits hardware ECC
z Totally 2GB memory space for 2 ranks, 16bits/32bits DDR3-800,
LPDDR2-800, LVDDR3-800
z Totally 3-channels SD/MMC interface to support MMC4.41, SD3.0,
SDIO3.0 or eMMC
z Dual-channels TFT LCD interface with 4-layers , 2048x1536 maximum
display size
z One-channels, 8bits BT656 interface, 16bits BT601 DDR interface and
10bits/12bits raw data interface with image preprocessor
z Audio interface: one 2ch I2S/PCM interface and SPDIF tx interface
z One USB OTG 2.0 and one USB Host2.0 interface and HSIC interface
z 10M/100M RMII ethernet interface
z GPS interface
z High-speed ADC interface and TS stream interface
z Lots of low-speed peripheral interface : 5I2C, 4UART, 2SPI,4 PWM
This document will provide guideline on how to use RK3188 correctly and
efficiently. The chapter 1 and chapter 2 will introduce the features, block
diagram, signal descriptions and system usage of RK3188, the chapter 3
through chapter 45 will describe the full function of each module in detail.
1.1 Features
1.1.1 MicroProcessor
z Quad-core ARM Cortex-A9 MPCore processor, a high-performance,
low-power and cached application processor
z Full implementation of the ARM architecture v7-A instruction set, ARM Neon
Advanced SIMD (single instruction, multiple data) support for accelerated
media and signal processing computation
z Superscalar, variable length, out-of-order pipeline with dynamic branch
High Performance and Low-power Processor for Digital Media Application
23
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RK3188 데이터시트, 핀배열, 회로
RK3188Technical Reference ManualRev 1.2
prediction, 8-stage pipeline
z Include VFPv3 hardware to support single and double-precision add,
subtract, divide, multiply and accumulate, and square root operations
z SCU ensures memory coherency between the four CPUs
z Integrated timer and watchdog timer per CPU
z Integrated 32KB L1 instruction cache , 32KB L1 data cache with 4-way set
associative
z 512KB unified L2 Cache
z Trustzone technology support
z Full coresight debug solution
„ Debug and trace visibility of whole systems
„ ETM trace support
„ Invasive and non-invasive debug
z Six separate power domains for every core to support internal power switch
and externally turn on/off based on different application scenario
„ PD_A9_0: 1st Cortex-A9 + Neon + FPU + L1 I/D Cache
„ PD_A9_1: 2nd Cortex-A9 + Neon + FPU + L1 I/D Cache
„ PD_A9_2: 3rd Cortex-A9 + Neon + FPU + L1 I/D Cache
„ PD_A9_3: 4th Cortex-A9 + Neon + FPU + L1 I/D Cache
„ PD_DBG: CoreSight-DK for Cortex-A9
„ PD_SCU: SCU + L2 Cache controller + L2 Dataram, and including
PD_A9_0, PD_A9_1, PD_A9_2, PD_A9_3, PD_DGB
z One isolated voltage domain to support DVFS
z Maximum frequency can be up to [email protected](Worst Case) or
[email protected](Typical Case).
1.1.2 Memory Organization
z Internal on-chip memory
„ 10KB BootRom
„ 32KB internal SRAM for security and non-security access, detailed size
is programmable
z External off-chip memoryķ
„ DDR3-800, 16/32bits data widths, 2 ranks, totally 2GB(max) address
space, maximum address space for one rank is also 2GB.
„ LPDDR2-800, 32bits data width, 2 ranks, totally 2GB(max) address
space, maximum address space for one rank is also 2GB.
„ Async SRAM/Nor Flash, 8/16bits data width,2banks
„ Async Nand Flash(include LBA Nand), 8/16bits data width, 4 banks,
60bits ECC
„ Sync ONFI Nand Flash , 8bits data width, 8 banks, 60bits ECC
1.1.3 Internal Memory
z Internal BootRom
„ Size : 10KB
„ Support system boot from the following device:
‹ 8bits/16bits Async Nand Flash
‹ 8bits ONFI Nand Flash
‹ SPI0 interface
‹ eMMC interface
‹ SDMMC interface
„ Support system code download by the following interface:
‹ USB OTG interface
‹ UART2Interface
High Performance and Low-power Processor for Digital Media Application
24
Free Datasheet http://www.datasheet4u.com/




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