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PDF ADRF6820 Data sheet ( Hoja de datos )
| Número de pieza | ADRF6820 | |
| Descripción | Quadrature Demodulator | |
| Fabricantes | Analog Devices | |
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Data Sheet
695 MHz to 2700 MHz, Quadrature Demodulator
with Integrated Fractional-N PLL and VCO
ADRF6820
FEATURES
I/Q demodulator with integrated fractional-N PLL
RF input frequency range: 695 MHz to 2700 MHz
Internal LO frequency range: 356.25 MHz to 2850 MHz
Input P1dB: 14.5 dBm at 1900 MHz RF
Input IP3: 37 dBm at 1900 MHz RF
Programmable HD3/IP3 trim
Single pole, double throw (SPDT) RF input switch
RF digital step attenuation range: 0 dB to 15 dB
Integrated RF tunable balun for single-ended 50 Ω input
Multicore integrated VCO
Demodulated 1 dB bandwidth: 600 MHz
4 selectable baseband gain and bandwidth modes
Digital programmable LO phase offset and dc nulling
Programmable via 3-wire serial port interface (SPI)
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular W-CDMA/GSM/LTE
Digital predistortion (DPD) receivers
Microwave point-to-point radios
FUNCTIONAL BLOCK DIAGRAM
RFIN0 29
15 14 13
SERIAL PORT
INTERFACE
RFIN1 22
2 3 8 9 23 25 26 28 38
DC/PHASE
CORRECTION
4 I+
5 I–
POLYPHASE
FILTER
QUAD
DIVIDER
35 LOIN+
34 LOIN–
PLL 39 REFIN
LDO
2.5V
LDO
VCO
1 19 30 36 31
VPOS_3P3
DC/PHASE
CORRECTION
27 33 40 10
DECL1 TO
DECL4
Figure 1.
11 21
VPOS_5V
6 Q–
7 Q+
GENERAL DESCRIPTION
The ADRF6820 is a highly integrated demodulator and synthesizer
ideally suited for next generation communication systems. The
feature rich device consists of a high linearity broadband I/Q
demodulator, an integrated fractional-N phase-locked loop (PLL),
and a low phase noise multicore, voltage controlled oscillator
(VCO). The ADRF6820 also integrates a 2:1 RF switch, an on-chip
tunable RF balun, a programmable RF attenuator, and two low
dropout (LDO) regulators. This highly integrated device fits
within a small 6 mm × 6 mm footprint.
The high isolation 2:1 RF switch and on-chip tunable RF balun
enable the ADRF6820 to support two single-ended, 50 Ω
terminated RF inputs. A programmable attenuator ensures
an optimal differential RF input level to the high linearity
demodulator core. The integrated attenuator offers an
attenuation range of 0 dB to 15 dB with a step size of 1 dB.
The ADRF6820 offers two alternatives for generating the
differential local oscillator (LO) input signal: externally via a
high frequency, low phase noise LO signal or internally via the
on-chip fractional-N synthesizer. The integrated synthesizer
enables continuous LO coverage from 356.25 MHz to 2850 MHz.
The PLL reference input can support a wide frequency range
because the divide or multiplication blocks can increase or
decrease the reference frequency to the desired value before it
is passed to the phase frequency detector (PFD).
When selected, the output of the internal fractional-N synthesizer
is applied to a divide-by-2 quadrature phase splitter. From the
external LO path, a 1× LO signal can be applied to the built-in
polyphase filter, or a 2× LO signal can be used with the divide-
by-2 quadrature phase splitter to generate the quadrature LO
inputs to the mixers.
The ADRF6820 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP package with an exposed paddle.
Performance is specified over the −40°C to +85°C temperature
range.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
ADRF6820
SYNTHESIZER/PLL SPECIFICATIONS
VPOS_5V = 5 V, VPOS_3P3 = 3.3 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, loop filter
bandwidth = 20 kHz, measured at LO output,
Table 3.
Parameter
PLL REFERENCE
Frequency
Amplitude
PFD FREQUENCY
INTERNAL VCO RANGE
REFERENCE SPURS
CLOSED-LOOP PERFORMANCE
20 kHz Loop Filter
Test Conditions/Comments
fREF = 153.6 MHz, fPFD = 38.4 MHz, fLO = 1809.6 MHz
fPFD/4
fPFD/2
fPFD × 1
fPFD × 2
fPFD × 3
fPFD × 4
fPFD × 5
fLO = 1809.6, fREF = 153.6 MHz, fPFD = 38.4 MHz
10 kHz offset
20 kHz offset
100 kHz offset
200 kHz offset
600 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
Min Typ
12
24
2850
4
<−100
<−100
−90.67
−95
−97
<−100
<−100
−94.7
−95.8
−113
−122.4
−136.5
−141.5
−153.3
−154.6
Max Unit
320
14
40
5700
MHz
dBm
MHz
MHz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. 0 | Page 5 of 44
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5 Page 
Data Sheet
8
7
6
5
BWSEL = 0
4
900MHz
1900MHz
2100MHz
2650MHz
3
2
1
0
–1
BWSEL = 2
–2
–3
–4
–5
–6
1.45
1.65
1.85
2.05
2.25
VCM (V)
Figure 15. Gain vs. Common-Mode Voltage (VCM) for fRF = 900 MHz, fRF =
1900 MHz, fRF = 2100 MHz, and fRF = 2650 MHz for BWSEL = 0 and BWSEL = 2
19
900MHz
18
1900MHz
2100MHz
17
BWSEL = 2
2650MHz
16
15
14
BWSEL = 0
13
12
11
10
9
1.45 1.65 1.85 2.05 2.25
VCM (V)
Figure 16. Input P1dB (IP1dB) vs. Common-Mode Voltage (VCM) for fRF =
900 MHz, fRF = 1900 MHz, fRF = 2100 MHz, and fRF = 2650 MHz
350
300
ICC (3.3V), INTERNAL LO
250
200
ICC (3.3V), EXTERNAL LO
150
100
50 ICC (5V)
0
1.45 1.55 1.65 1.75 1.85 1.95 2.05 2.15 2.25
VCM (V)
Figure 17. Current Consumption (ICC) vs. Common-Mode Voltage (VCM),
Internal and External LO, fRF = 900 MHz, fRF = 1900 MHz, fRF = 2100 MHz, fRF =
2100 MHz, and fRF = 2650 MHz
ADRF6820
0
TA = –40°C
–20
TA = +25°C
TA = +85°C
–40
1kHz OFFSET
–60
–80
–100
10kHz OFFSET
50kHz OFFSET
–120
–140
1MHz OFFSET
–160
10MHz OFFSET
–180
2.85 3.35 3.85 4.35 4.85 5.35
VCO FREQUENCY (GHz)
Figure 18. Open-Loop Phase Noise for 1 kHz, 10 kHz, 50 kHz, 1 MHz, and
10 MHz Offsets
–80
–85
TA = –40°C
TA = +25°C
–90 TA = +85°C
–95
–100
–105
100kHz OFFSET
–110
–115
–120
–125
500kHz OFFSET
–130
–135
–140
800kHz OFFSET
–145
–150
40MHz OFFSET
–155
–160
–165
2.85 3.35 3.85 4.35 4.85 5.35
VCO FREQUENCY (GHz)
Figure 19. Open-Loop Phase Noise for 100 kHz, 500 kHz, 800 kHz, and
40 MHz Offsets
–90
–95
–100
–105
TA = –40°C
TA = +25°C
TA = +85°C
50kHz OFFSET
–110
–115
100kHz OFFSET
–120
200kHz OFFSET
–125
–130
500kHz OFFSET
–135
–140
–145
–150
1MHz OFFSET
–155
–160
40MHz OFFSET
1425 1550 1675 1800 1925 2050 2175 2300 2425 2550 2675 2800
LO FREQUENCY (MHz)
Figure 20. Closed-Loop Phase Noise vs. LO Frequency, 20 kHz Bandwidth
Loop Filter, Measured with DIV4_EN = 1 (Divide by 2)
Rev. 0 | Page 11 of 44
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