파트넘버.co.kr ADF4159 데이터시트 PDF


ADF4159 반도체 회로 부품 판매점

Fractional-N Frequency Synthesizer



Analog Devices 로고
Analog Devices
ADF4159 데이터시트, 핀배열, 회로
Data Sheet
Direct Modulation/Fast Waveform Generating,
13 GHz, Fractional-N Frequency Synthesizer
ADF4159
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 13 GHz
High and low speed FMCW ramp generation
25-bit fixed modulus allows subhertz frequency resolution
PFD frequencies up to 110 MHz
Normalized phase noise floor of −224 dBc/Hz
FSK and PSK functions
Sawtooth, triangular, and parabolic waveform generation
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay, frequency readback, and interrupt functions
Programmable phase control
2.7 V to 3.45 V analog power supply
1.8 V digital power supply
Programmable charge pump currents
3-wire serial interface
Digital lock detect
ESD performance: 3000 V HBM, 1000 V CDM
The ADF4159 is a 13 GHz, fractional-N frequency synthesizer
with modulation and both fast and slow waveform generation
capability. The part uses a 25-bit fixed modulus, allowing subhertz
frequency resolution.
The ADF4159 consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. The Σ-Δ-based fractional interpolator allows
programmable fractional-N division. The INT and FRAC registers
define an overall N divider as N = INT + (FRAC/225).
The ADF4159 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. Frequency sweep
modes are also available to generate various waveforms in the
frequency domain, for example, sawtooth and triangular wave-
forms. The ADF4159 features cycle slip reduction circuitry, which
enables faster lock times without the need for modifications to
the loop filter.
APPLICATIONS
FMCW radars
Communications test equipment
Communications infrastructure
Control of all on-chip registers is via a simple 3-wire interface. The
ADF4159 operates with an analog power supply in the range of
2.7 V to 3.45 V and a digital power supply in the range of 1.62 V
to 1.98 V. The device can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD SDVDD
VP
RSET
ADF4159
REFIN
×2
DOUBLER
5-BIT
R COUNTER
÷2
DIVIDER
HIGH-Z
MUXOUT
OUTPUT
MUX
CE
TXDATA
DGND
SDOUT
DVDD
RDIV
NDIV
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
+ PHASE
FREQUENCY
DETECTOR
REFERENCE
SW2
CHARGE
PUMP
CSR
FAST LOCK
SWITCH
CP
SW1
N COUNTER
+
RFINA
RFINB
CLK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION
VALUE
MODULUS
225 VALUE
INTEGER
VALUE
AGND
DGND
SDGND
Figure 1.
CPGND
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/


ADF4159 데이터시트, 핀배열, 회로
ADF4159
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 10
Reference Input Section............................................................. 10
RF Input Stage............................................................................. 10
RF INT Divider........................................................................... 10
25-Bit Fixed Modulus ................................................................ 10
INT, FRAC, and R Counter Relationship................................ 10
R Counter .................................................................................... 10
Phase Frequency Detector (PFD) and Charge Pump............ 11
MUXOUT and Lock Detect...................................................... 11
Input Shift Register..................................................................... 11
Program Modes .......................................................................... 11
Register Maps .................................................................................. 12
FRAC/INT Register (R0) Map.................................................. 14
LSB FRAC Register (R1) Map................................................... 15
R Divider Register (R2) Map .................................................... 16
Function Register (R3) Map...................................................... 18
Clock Register (R4) Map ........................................................... 20
REVISION HISTORY
6/13—Rev. A to Rev. B
Changed PFD Antibacklash Pulse from 3 ns to 1 ns in Phase
Frequency Detector (PFD) and Charge Pump Section ............. 11
Changes to Charge Pump Current Setting Section and
Reference Doubler Section ............................................................ 16
Changes to Negative Bleed Current Enable Section and Loss of
Lock (LOL) Section ........................................................................ 18
5/13—Revision A: Initial Version
Data Sheet
Deviation Register (R5) Map .................................................... 21
Step Register (R6) Map.............................................................. 22
Delay Register (R7) Map ........................................................... 23
Applications Information .............................................................. 24
Initialization Sequence .............................................................. 24
RF Synthesizer Worked Example ............................................. 24
Reference Doubler...................................................................... 24
Cycle Slip Reduction for Faster Lock Times........................... 24
Modulation.................................................................................. 25
Waveform Generation ............................................................... 25
Waveform Deviations and Timing........................................... 26
Single Ramp Burst...................................................................... 26
Single Triangular Burst.............................................................. 26
Single Sawtooth Burst ................................................................ 26
Sawtooth Ramp........................................................................... 26
Triangular Ramp ........................................................................ 26
FMCW Radar Ramp Settings Worked Example...................... 26
Activating the Ramp .................................................................. 27
Other Waveforms ....................................................................... 27
Ramp Complete Signal to MUXOUT ..................................... 30
Interrupt Modes and Frequency Readback ............................ 31
Fast Lock Mode .......................................................................... 32
Spur Mechanisms ....................................................................... 33
Filter Design Using ADIsimPLL .............................................. 33
PCB Design Guidelines for the Chip Scale Package.............. 33
Application of the ADF4159 in FMCW Radar........................... 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
Rev. B | Page 2 of 36
Free Datasheet http://www.datasheet4u.com/




PDF 파일 내의 페이지 : 총 30 페이지

제조업체: Analog Devices

( analogs )

ADF4159 data

데이터시트 다운로드
:

[ ADF4159.PDF ]

[ ADF4159 다른 제조사 검색 ]




국내 전력반도체 판매점


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877

[ 홈페이지 ]

IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈

( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )

전력반도체 문의 : 010-3582-2743



일반적인 전자부품 판매점


디바이스마트

IC114

엘레파츠

ICbanQ

Mouser Electronics

DigiKey Electronics

Element14


관련 데이터시트


ADF4150

Fractional-N/Integer-N PLL Synthesizer - Analog Devices



ADF4150HV

Fractional-N/Integer-N PLL Synthesizer - Analog Devices



ADF4151

Fractional-N/Integer-N PLL Synthesizer - Analog Devices



ADF4152HV

Fractional-N/ Integer N PLL Synthesizer - Analog Devices



ADF4153

Fractional-N Frequency Synthesizer - Analog Devices



ADF4153A

Fractional-N Frequency Synthesizer - Analog Devices



ADF4154

Fractional-N Frequency Synthesizer - Analog Devices



ADF4155

Integer-N/Fractional-N PLL Synthesizer - Analog Devices



ADF4156

6.2 GHz Fractional-N Frequency Synthesizer - Analog Devices