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Super Sequencer



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Analog Devices
ADM1069 데이터시트, 핀배열, 회로
Data Sheet
Super Sequencer with Margining Control
ADM1069
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 4 voltage rails
4 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead, 7 mm × 7 mm LQFP and 40-lead,
6 mm × 6 mm LFCSP packages
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
FUNCTIONAL BLOCK DIAGRAM
REFIN REFOUT REFGND SDA SCL A1 A0
ADM1069
VREF
12-BIT
SAR ADC
CLOSED-LOOP
MARGINING SYSTEM
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
SMBus
INTERFACE
EEPROM
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
VOUT VOUT VOUT VOUT
DAC DAC DAC DAC
VDD
ARBITRATOR
PDOGND
VDDCA P
DAC1 DAC2 DAC3 DAC4
VCCP
Figure 1.
GND
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1069 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1069 integrates a 12-bit analog-to-
digital converter (ADC) and four 8-bit voltage output digital-to-
analog converters (DACs). These circuits can implement a closed-
loop margining system that enables supply adjustment by altering
either the feedback node or reference of a dc-to-dc converter
using the DAC outputs.
For more information about the ADM1069 register map, refer
to the AN-721 Application Note.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


ADM1069 데이터시트, 핀배열, 회로
ADM1069* Product Page Quick Links
Last Content Update: 08/30/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• ADM1069 Evaluation Board
Documentation
Application Notes
• AN-0973: Erasing and Programming the Sequencing
Engine EEPROM
• AN-0975: Automatic Generation of State Diagrams for the
ADM1062 to ADM1069 Using Graphviz
• AN-0997: Ping-Pong Configuration Guide for ADM1062 to
ADM1069 Devices
• AN-1001: Checksum Calculations
• AN-1009: Block Erasing, Reading and Writing to the
ADM106x EEPROM
• AN-1086: Using an ADM106x in a Hot Swap Application
• AN-721: ADM1068/ADM1069/ADM1168/ADM1169
Configuration Registers
• AN-722: Watchdog Detection Using the ADM106x
• AN-723: Interrupt Generation Using the ADM106x
• AN-780: Monitoring Negative Voltages with the ADM1062
to ADM1069 Super Sequencers
• AN-781: Monitoring Additional Supplies with the
ADM1062-ADM1069 Super Sequencers™
• AN-897: ADC Readback Code
Data Sheet
• ADM1069: Super Sequencer with Margining Control Data
Sheet
User Guides
• SuperSequencer Documentation
• UG-404: USB-SDP-CABLEZ Serial Interface Board
Software and Systems Requirements
• ADMxxxx Common Run-Time
• SuperSequencer Software
Reference Materials
Informational
• Optical and High Speed Networking ICs
Product Selection Guide
• Supervisory Devices Complementary Parts Guide for Altera
FPGAs
• Supervisory Devices Complementary Parts Guide for Xilinx
FPGAs
Solutions Bulletins & Brochures
• Power Supply Sequencing Bulletin (2007)
Design Resources
• ADM1069 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all ADM1069 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.




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