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PDF M82C59A Data sheet ( Hoja de datos )
| Número de pieza | M82C59A | |
| Descripción | MSM82C59A | |
| Fabricantes | OKI | |
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E2O0021-27-X3
¡ Semiconductor¡ Semiconductor
MTShMis8v2eCr5si9oAn-:2JRaSn./G19S9/8JS
Previous version: Aug. 1996
MSM82C59A-2RS/GS/JS
PROGRAMMABLE INTERRUPT CONTROLLER
GENERAL DESCRIPTION
The MSM82C59A-2 is a programmable interrupt for use in MSM80C85AH and MSM80C86A-
10/88A-10 microcomputer systems.
Based on CMOS silicon gate technology, this device features an extremely low standby current
of 100mA (max.) in chip non-selective status. During interrupt control status, the power
consumption is very low with only 5 mA (max.) being required.
Internally, the MSM82C59A-2 can control priority interrupts up to 8 levels, and can be
expanded up to 64 levels by cascade connection of a number of devices.
FEATURES
• Silicon gate CMOS technology for high speed and low power consumption
• 3 V to 6 V single power supply
• MSM80C85AH system compatibility (MAX5 MHz)
• MSM80C86A-10/88A-10 system compatibility (MAX8 MHz)
• 8-level priority interrupt control
• Interrupt levels expandable up to 64 levels
• Programmable interrupt mode
• Maskable interrupt
• Automatically generated CALL code (85 mode)
• TTL compatible
• 28-pin Plastic DIP (DIP28-P-600-2.54): (Product name: MSM82C59A-2RS)
• 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C59A-2JS)
www.D•at3a2S-hpeient4PU.lcaosmtic SSOP (SSOP32-P-430-1.00-K): (Product name: MSM82C59A-2GS-K)
1/28Free Datasheet http://www.datasheet4u.com/
1 page  
¡ Semiconductor
MSM82C59A-2RS/GS/JS
AC CHARACTERISTICS
Parameter
Address Setup Time (to RD)
Address Hold Time (after RD)
RD/INTA Pulse Width
Address Setup Time (to WR)
Address Hold Time (after WR)
WR Pulse Width
Data Setup Time (to WR)
Data Hold Time (after WR)
IR Input Width(Low)
CAS Input Setup Time (to INTA) (Slave)
End of RD to Next RD
End of INTA to Next INTA
End of WR to Next WR
End of Command to Next Command
Data Valid Following RD/ INTA
Data Floating Following RD/ INTA
INT Output Delay Time
CAS Valid Following 1 st. INTA (master)
EN Active Following RD/INTA
EN Inactive Following RD/ INTA
Data Valid after Address
Data Valid after CAS
Symbol
tAHRL
tRHAX
tRLRH
tAHWL
tWHAX
tWLWH
tDVWH
tWHDX
tJLJH
tCVIAL
Min.
10
5
160
0
0
190
160
0
100
40
Max.
—
—
—
—
—
—
—
—
—
—
Ta = –40°C - +85°C, VCC = 5 V ± 10%
Unit TEST Conditions
ns
ns — Read INTA timing
ns
ns
—
ns — Write timing
ns
ns
ns — INTA sequence
ns
tRHRL 160 —
ns
tWHWL 190 —
ns
—
Other timing
tCHCL 400 —
ns
tRLDV — 120 ns
1
tRHDZ 10 85 ns
2
tJHIH — 300 ns
1
tIALCV — 360 ns
tRLEL
— 100 ns
1 Delay times
1
tRHEH — 150 ns
1
tAHDV — 200 ns
1
tCVDV — 200 ns
1
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AC Test Circuits
A.C. Testing Input, Output Waveform
Output from
Device under Test
V1
R1
Test Point
Input
VIH+0.4 V
1.5V
VIL–0.4 V
Output
VOH
1.5 V
VOL
R2 C1*
A. C. Testing: All input signals must switch between
VIL–0.4 V and VIH+0.4 V.
* Includes Stray and Jig Capacitance
TR and TF must be less than of equal to 15 ns.
Test Condition Definition Table
Test Condition V1 R1 R2 C1
1 1.7 V 523 W Open 100 pF
2 4.5 V 1.8k W 1.8k W 30 pF
5/28Free Datasheet http://www.datasheet4u.com/
5 Page 
¡ Semiconductor
MSM82C59A-2RS/GS/JS
(v) A further two INTA pulses are then sent to the MSM82C59A-2 from the CPU by this
CALL instruction.
(vi) These two INTA pulses result in a preprogrammed subroutine address being sent from
the MSM82C59A-2 to the data bus. The lower 8-bit address is released by the first INTA
pulse, and the higher 8-bit address is released by the second pulse.
The Falling Edge of the second INTA signal sets the ISR bit with the highest priority,
and the Rising Edge of it resets the IRR bit.
(vii) 3-byte CALL instructions are thus released by the MSM82C59A-2. In Automatic End
Of Interrupt (AEOI) mode, the IRS bit is reset at the end of the third INTA pulse. In other
cases, the ISR bit remains set until reception of a suitable EOI command at the end of
the interrupt routine.
The procedure for the 86 system (MSM80C86A-10/88A-10) is identical to the first three
steps of the 85 system. The subsequent steps are described below.
(iv) Upon reception of the INTA signal from the CPU, the ISR bit with the highest priority
is set, and the corresponding IRR bit is reset. In this cycle, the MSM82C59A-2 sets the
data bus to high impedance without driving the Data Bus.
(v) The CPU generates a second INTA output pulse, resulting in an 8-bit pointer to the data
bus by the MSM82C59A-2.
The Falling Edge of the INTA signal sets the ISR bit with the highest priority, and the
Rising Edge of it resets the IRR bit.
(vi) This completes the interrupt cycle. In AEOI mode, the ISR bit is reset at the end of the
second INTA pulse. In other cases, the ISR bit remains set until reception of 3 suitable
EOI command at the end of the interrupt routine.
If the interrupt request is canceled prior to step (iv), that is, before the first INTA pulse has
been received, the MSM82C59A-2 operates as if a level 7 interrupt has been received, and
the vector byte and CAS line operate as if a level 7 interrupt has been requested.
(3) Interrupt Sequence Output
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85 Mode (MSM80C85AH)
The sequence in this case consists of three INTA pulses. A CALL operation code is released
to the data bus by the first INTA pulse.
CALL Code
Contents of the First Interrupt Vector Byte
D7 D6 D5 D4 D3
1 10 01
D2 D1 D0
10 1
The lower address of the interrupt service routine is released to the data bus by the second
INTApulse. If A5-A7 are programmed with an address interval of 4, A0-A4 are automatically
inserted. And if A6 and A7 are programmed at an address interval of 8, A0-A5 are
automatically inserted.
Contents of the second interrupt vector byte
11/28Free Datasheet http://www.datasheet4u.com/
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