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PDF 74ALS169B Data sheet ( Hoja de datos )
| Número de pieza | 74ALS169B | |
| Descripción | Synchronous Four-Bit Up/Down Counters | |
| Fabricantes | Fairchild Semiconductor | |
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April 1984
Revised April 2000
DM74ALS169B
Synchronous Four-Bit Up/Down Counters
General Description
These synchronous presettable counters feature an inter-
nal carry look ahead for cascading in high speed counting
applications. The DM74ALS169B is a four-bit binary up/
down counter. The carry output is decoded to prevent
spikes during normal mode of counting operation. Synchro-
nous operation is provided so that outputs change coinci-
dent with each other when so instructed by count enable
inputs and internal gating. This mode of operation elimi-
nates the output counting spikes which are normally asso-
ciated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive going) edge of clock input waveform.
These counters are fully programmable; that is, the outputs
may each be preset either HIGH or LOW. The load input
circuitry allows loading with carry-enable output of cas-
caded counters. As loading is synchronous, setting up a
low level at the load input disables the counter and causes
the outputs to agree with the data inputs after the next
clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count enable inputs (P and T) must be LOW to count.
The direction of the count is determined by the level of the
up/down input. When the input is HIGH, the counter counts
UP; when LOW, it counts DOWN. Input T is fed forward to
enable the carry outputs. The carry output thus enabled will
produce a low level output pulse with a duration approxi-
mately equal to the high portion of the QA output when
counting UP, and approximately equal to the low portion of
the QA when counting DOWN. This low level overflow carry
pulse can be used to enable successively cascaded
stages. Transitions at the enable P or T inputs are allowed
regardless of the level of the clock input.
The control functions for these counters are fully synchro-
nous. Changes at control inputs (enable P, enable T, load,
up/down) which modify the operating mode have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
s Improved AC performance over Schottky and low power
Schottky counterparts
s Synchronously programmable
s Internal look ahead for fast counting
s Carry output for n-bit cascading
s Synchronous counting
s ESD inputs
Ordering Code:
Order Number Package Number
Package Description
DM74ALS169BM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS169BN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006207
www.fairchildsemi.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C
Symbol
Parameter
Conditions
Min Typ
VIK Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
VCC = 4.5V, II = −18 mA
IOH = −0.4 mA
VCC = 4.5V to 5.5V
VCC = 4.5V
IOL = 8 mA
VCC − 2
0.35
II Input Current @ Max
Input Voltage
VCC = 5.5V, VIH = 7V
IIH HIGH Level Input Current
IIL LOW Level Input Current
IO Output Drive Current
ICC Supply Current
VCC = 5.5V, VIH = 2.7V
VCC = 5.5V, VIL = 0.4V
VCC = 5.5V, VO = 2.25V
VCC = 5.5V
−30
15
Max
−1.5
Units
V
V
0.5 V
0.1
20
−0.2
−112
25
mA
µA
mA
mA
mA
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
fMAX
Maximum Clock Frequency
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
VCC = 4.5V to 5.5V
RL = 500Ω
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
CL = 50 pF
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
From
Clock
To Min
40
Ripple Carry
3
Clock
Clock
Clock
Ripple Carry
Any Q
Any Q
6
2
5
Max
20
Units
MHz
ns
20 ns
15 ns
20 ns
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
En T
Ripple Carry
2
13 ns
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
En T
Ripple Carry
3
16 ns
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
U/D (Note 3) Ripple Carry
5
19 ns
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
U/D (Note 3) Ripple Carry
5
19 ns
Note 3: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level
of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is
maximum, the ripple carry output will be out of phase.
5 www.fairchildsemi.com
Free Datasheet http://www.datasheet4u.com/
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