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Power MOSFET
SiHG20N50C
Vishay Siliconix
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) (Ω)
Qg (Max.) (nC)
Qgs (nC)
Qgd (nC)
Configuration
560
VGS = 10 V
76
21
34
Single
0.270
D
TO-247AC
G
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• Low Figure-of-Merit Ron x Qg
• 100 % Avalanche Tested
• High Peak Current Capability
• dV/dt Ruggedness
• Improved Trr/Qrr
• Improved Gate Charge
• High Power Dissipations Capability
• Compliant to RoHS Directive 2002/95/EC
S
D
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
Lead (Pb)-free and Halogen-free
TO-247AC
SiHG20N50C-E3
SiHG20N50C-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)e
Pulsed Drain Currenta
Linear Derating Factor
VGS at 10 V
TC = 25 °C
TC = 100 °C
VDS
VGS
ID
IDM
Single Pulse Avalanche Energyb
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
EAS
PD
dV/dt
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
TJ, Tstg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 Ω, IAS = 17 A.
c. ISD ≤ 18 A, dI/dt ≤ 380 A/μs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. Limited by maximum junction temperature.
LIMIT
500
± 30
20
11
80
1.8
361
250
5
- 55 to + 150
300d
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
RthJA
RthJC
TYP.
-
-
MAX.
40
0.5
UNIT
V
A
W/°C
mJ
W
V/ns
°C
UNIT
°C/W
Document Number: 91382
S11-0440-Rev. C, 14-Mar-11
www.vishay.com
1
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vFishary.coem/deoc?910D00 a t a s
SiHG20N50C
Vishay Siliconix
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
10-4
Single Pulse
10-3
10-2
0.1
Pulse Time (s)
Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case (TO-247)
1
VDS
VGS
Rg
RD
D.U.T.
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
+- VDD
Fig. 11a - Switching Time Test Circuit
VDS
VDS
tp
VDD
IAS
Fig. 12b - Unclamped Inductive Waveforms
VDS
90 %
10 %
VGS
td(on) tr
td(off) tf
Fig. 11b - Switching Time Waveforms
VDS
Vary tp to obtain
required IAS
Rg
10 V
tp
L
D.U.T
IAS
0.01 Ω
+
- VDD
Fig. 12a - Unclamped Inductive Test Circuit
10 V
QGS
VG
QG
QGD
Charge
Fig. 13a - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
12 V
50 kΩ
0.2 µF
0.3 µF
+
D.U.T. - VDS
VGS
3 mA
IG ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
Document Number: 91382
S11-0440-Rev. C, 14-Mar-11
www.vishay.com
5
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000