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74HCT4510 반도체 회로 부품 판매점

BCD up/down counter



NXP Semiconductors 로고
NXP Semiconductors
74HCT4510 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
www.DataSheet.net/
74HC/HCT4510
BCD up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990
Datasheet pdf - http://www.DataSheet4U.co.kr/


74HCT4510 데이터시트, 핀배열, 회로
Philips Semiconductors
BCD up/down counter
Product specification
74HC/HCT4510
FEATURES
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4510 are high-speed Si-gate CMOS
devices and are pin compatible with the “4510” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4510 are edge-triggered synchronous
up/down BCD counters with a clock input (CP), an
up/down count control input (UP/DN), an active LOW
count enable input (CE), an asynchronous active HIGH
parallel load input (PL), four parallel inputs (D0 to D3), four
parallel outputs (Q0 to Q3), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
Information on D0 to D3 is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. With PL LOW, the
counter changes on the LOW-to-HIGH transition of CP if
CE is LOW. UP/DN determines the direction of the count,
HIGH for counting up, LOW for counting down. When
counting up, TC is LOW when Q0 and Q3 are HIGH and CE
is LOW. When counting down, TC is LOW when Q0 to Q3
and CE are LOW. A HIGH on MR resets the counter (Q0 to
Q3 = LOW) independent of all other input conditions.
Logic equation for terminal count: TC = CE . {(UP/DN) . Q0 . Q3+(UP/DN) . Q0 . Q1 . Q2 . Q3}
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
tPHL/ tPLH
fmax
CI
CPD
PARAMETER
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per package
CONDITIONS
TYPICAL
HC HCT
www.DataSheet.net/
CL = 15 pF; VCC = 5 V 21
57
23
58
3.5 3.5
notes 1 and 2
50 53
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC 1.5 V
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Datasheet pdf - http://www.DataSheet4U.co




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