PDF W641GG2JB Data sheet ( Hoja de datos )

Número de pieza	W641GG2JB
Descripción	1-Gbit GDDR3 Graphics SDRAM
Fabricantes	Winbond
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No Preview Available ! www.DataSheet.co.kr W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Table of Contents 1. GENERAL DESCRIPTION .......................................................................................................... 6 2. FEATURES .................................................................................................................................. 7 3. PIN CONFIGURATION ................................................................................................................ 8 3.1 Ballout 1-CS Non-Merged Mode (Top View, MF=0)............................................................................. 8 3.2 Ballout 2-CS Non-Merged Mode (Top View, MF=0)............................................................................. 9 3.3 Ballout Merged Mode (Top View, MF=0) ........................................................................................... 10 4. PIN DESCRIPTION.................................................................................................................... 11 4.1 Signal Description.............................................................................................................................. 11 4.2 Addressing ........................................................................................................................................ 12 5. STATE DIAGRAM ..................................................................................................................... 13 5.1 State Diagram for One Activated Bank............................................................................................... 13 5.1.1 State diagram for one bank .............................................................................................................................13 5.1.2 Function Truth Table for more than one Activated Bank..................................................................................14 5.1.2.1 Function Truth Table ...................................................................................................................................................14 5.1.3 Function Truth Table for CKE ..........................................................................................................................15 5.2 Functional Block Diagram in 1-CS Mode ........................................................................................... 16 5.3 Functional Block Diagram in 2-CS Mode ........................................................................................... 17 6. FUNCTIONAL DESCRIPTION................................................................................................... 18 6.1 System Configurations....................................................................................................................... 18 6.1.1 System Configurations in 1-CS Mode and 2-CS Mode ...................................................................................18 6.1.2 Initialization in 1– CS mode .............................................................................................................................19 6.1.3 Initialization in 2– CS mode .............................................................................................................................20 6.1.3.1 Power Up Sequence ...................................................................................................................................................21 .2 Mirror Function .................................................................................................................................... 22 6.2.1 Ball Assignment with Mirror Function ..............................................................................................................22 6.3 Commands ........................................................................................................................................ 23 6.3.1 Command Overview for 1-CS mode ................................................................................................................23 6.3.2 Command Overview for 2-CS mode ................................................................................................................24 6.3.3 Description of Command .................................................................................................................................25 6.3.4 Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent AP .............28 6.4 Boundary Scan .................................................................................................................................. 28 6.4.1 General Description .........................................................................................................................................28 6.4.2 Disabling the scan feature ...............................................................................................................................28 6.4.2.1 Internal Block Diagram (Reference only) ....................................................................................................................29 6.4.2.2 Boundary Scan Exit Order...........................................................................................................................................29 6.4.2.3 Scan Pin Description ...................................................................................................................................................30 6.4.2.4 Scan DC Electrical Characteristics and Operating Condition.......................................................................................30 6.4.2.5 Scan Capture Timing...................................................................................................................................................31 Publication Release Date: Apr, 22, 2011 - 1 - Revision A01-002 Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.2.1.1 Power & DC Operation Conditions (0 °C ≤ Tc ≤ 105 °C) ............................................................................................93 7.3 DC & AC Logic Input Levels............................................................................................................... 94 7.3.1 DC & AC Logic Input Levels (0 °C ≤ Tc ≤ 105 °C) ..........................................................................................94 7.4 Differential Clock DC and AC Levels .................................................................................................. 95 7.4.1 Differential Clock DC and AC Input conditions (0 °C ≤ Tc ≤ 105°C) ...............................................................95 7.5 Output Test Conditions ...................................................................................................................... 95 7.6 Pin Capacitances............................................................................................................................... 96 7.6.1 Pin Capacitances (VDDQ = 1.8 V, TA = 25°C, f = 1 MHz) ..............................................................................96 7.7 Driver current characteristics ............................................................................................................. 96 7.7.1 Driver IV characteristics at 40 Ohms................................................................................................................96 7.7.1.1 40 Ohm Driver Pull-Down and Pull-up Characteristics................................................................................................96 7.7.1.2 Programmed Driver IV Characteristics at 40 Ohm .......................................................................................................97 7.8 Termination current characteristics .................................................................................................... 97 7.8.1 Termination IV Characteristic at 60 Ohms .......................................................................................................97 7.8.1.1 60 Ohm Active Termination Characteristic..................................................................................................................98 7.8.1.2 Programmed Terminator Characteristics at 60 Ohm....................................................................................................98 7.8.2 Termination IV Characteristic at 120 Ohms .....................................................................................................99 7.8.2.1 120 Ohm Active Termination Characteristic................................................................................................................99 7.8.2.2 Programmed Terminator Characteristics of 120 Ohm................................................................................................100 7.8.3 Termination IV Characteristic at 240 Ohms ...................................................................................................100 7.8.3.1 240 Ohm Active Termination Characteristic..............................................................................................................100 7.8.3.2 Programmed Terminator Characteristics at 240 Ohm ...............................................................................................101 7.9 Operating Current Ratings............................................................................................................... 102 7.10 AC Timings .................................................................................................................................... 103 8. PACKAGE SPECIFICATION................................................................................................... 106 9. ORDERING INFORMATION.................................................................................................... 107 10. REVISION HISTORY ............................................................................................................. 108 -5- Publication Release Date: Apr, 22, 2011 Revision A01-002 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page www.DataSheet.co.kr W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 4. PIN DESCRIPTION 4.1 Signal Description Ball Type Detailed Function CLK, CLK# Input Clock:CLK and CLK# are differential clock inputs. Command and address inputs are latched on the rising edge of CLK. All latencies are referenced to CLK. CLK and CLK# are not internally terminated. CKE Input Clock Enable:CKE High activates and CKE Low deactivates internal clock, device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operations (all banks idle), or Active Power-Down (row active in any bank). CKE is synchronous for Power-Down entry and exit and for Self Refresh entry. CKE must be maintained High throughout READ, WRITE and bus snoop bursts. Input buffers excluding CLK, CLK# and CKE are disabled during Power-Down. Input buffers excluding CKE are disabled during Self Refresh. The value of CKE latched at power-up with RES going High determines the termination value of the address and command inputs. CS0#,CS1# Input Chip Select:Chip Select: CS# Low enables, and CS# High disables the command decoder. All commands except DTERDIS are masked when CS# is registered High, but internal command execution continues. CS# provides for individual device selection on memory channels with multiple memory devices. CS# is considered part of the command code. In 1-CS mode only CS0# is available. In 2-CS mode both CS0# and CS1# are available, and CS0# is exclusively used for Mode Register or Extended Mode Register programming and self refresh entry. RAS#,CAS#, WE# Input Command Inputs:Command inputs: RAS#, CAS# and WE# (along with CS0# or CS1#) define the command to be entered. BA0-BA2 Input Bank Address Inputs:BA0-BA2 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA0-BA2 also determine which Mode Register or Extended Mode Register is accessed with a MODE REGISTER SET command. A0-A11 (A12) Input Address Inputs:Address inputs: provide the row address for ACTIVE commands and the column address and auto precharge function (A8) for READ and WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 Low, bank selected by BA0- BA2) or all banks (A8 High). The address inputs also provide the op-code during an MODE REGISTER SET command. A12 is the MSB row address in 1-CS mode. DQ0-DQ31 DM0-DM3 RDQS0- RDQS3 WDQS0- WDQS3 ZQ I/O Data Inputs/Outputs:Data Input/Output: 32 bit data bus Input Output Input Data Masks:Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled High along with that input data during a WRITE access. DM is sampled on the rising and falling edges of WDQS. DM0 is associated with DQ0-DQ7, DM1 with DQ8-DQ15, DM2 with DQ16-DQ23 and DM3 with DQ24-DQ31. Read Data Strobes: Output with read data. RDQS is edge-aligned with read data. RDQS0 is associated with DQ0-DQ7, RDQS1 with DQ8-DQ15, RDQS2 with DQ16-DQ23 and RDQS3 with DQ24-DQ31. Input Write Data Strobes:WRITE Data strobe: Input with write data. WDQS is center-aligned to the input data. WDQS0 is associated with DQ0-DQ7, WDQS1 with DQ8-DQ15, WDQS2 with DQ16-DQ23 and WDQS3 with DQ24-DQ31. Reference ODT Impedance Reference: The ZQ ball is used to control the ODT impedance. - 11 - Publication Release Date: Apr, 22, 2011 Revision A01-002 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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