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PE12016G / PE12024G
December 15, 2005 Version 1.7
Incremental Encoder
Features:
• Functional and pincompatible with obsolete
TI CF32007NW/NT / THCT12016 /
THCT 12024 / LS2000
• 5 V and 3.3 V Operation
• 0.6u CMOS Process
• Direction discriminator
• Pulse width measurement
• Frequency measurement
• Cascadable (PE12016G only)
• TTL compatible
• 8 Bit parallel tristateable Bus
• Simple read & write procedure
• High speed 20 MHz clock operation
• PE12016G ONLY: 1:1 Replacement for
LS2000AN
• PE12024G ONLY: 24-Bit resolution,
separate UA0 counter reset
• WEEE & RoHS Compliant according
DIRECTIVE 2002/95/EC
(Green Package Material)
PE12016G
PDIP28-600 Mil
1
CS
28
VCC
RD UP
D0 DOWN
D1 WE
D2 RESET
D3 A0
GND
CLK
D4 UA2
D5 UA1
D6 M0
D7 M1
BORROW
M2
CARRY READY
GND KLI-KLO
14 15
PE12024G
PDIP24-300 Mil
1 24
CS VCC
RD UA0
D0 A1
D1 WE
D2 RESET
D3 A0
GND CLK
D4 UA2
D5 UA1
D6 M0
D7 M1
GND
12
M2
13
Description:
The PE12016G/12024G INCREMENTAL
ENCODER INTERFACE can independently
determine the direction or displacement of a
mechanical device or axis based on two input
signals from transducers in quadrature.
Alternatively, it can measure a pulse width using
a known clock rate, or a frequency, by counting
input pulses over a
known time interval. It includes one 16-bit or 24-
bit counter which may also be used separately
(PE12016G only). The PE12016G may be
cascaded to provide accuracy greater than 16-
bits. Both devices are designed for use in many
microprocessor-based systems.
December 15, 2005 (Version 1.7)
Seite 1 / 25
PE12016G/24G
www.DataSheet4U.net
December 15, 2005 Version 1.7
PE12016G / PE12024G
Incremental Encoder
Availability:
The PE12016G/24G is available as replacement
IC or Netlist IP Core, fully compatible with the
obsolete TI CF32007NW/NT functionality. The
replacement IC is packaged within the popular
PDIP28-600 Mil (PE12016G) and the PDIP24-
300 Mil package (PE12024G).
The IP Core can be targeted to any desired
FPGA/CPLD or ASIC Technology and is
delivered within the according netlist format. The
database has been proven in a co-emulation
together with the reference part by stimulating
both devices with the same inputs and observing
the identical results on the outputs.
Ressource Usage IP Core:
Gate count for ASIC Technologies is 1700 Gates. For CPLDs 128 Macrocells are needed, resulting
in a Xilinx XC95144 CPLD
Differences:
The PE12016G/24G has some minor
enhancements. UA1 and UA2 are synchronized
with the clock, eliminating the need to place a
discrete ACT74 type Flipflop in front of these
signals. Due to this feature a latency of one clock
cycle is introduced, resulting worst case in a +/-1
counter difference.
The output driver capability is slightly decreased.
Pullups are on the following pins: /A1, /UP,
/DOWN and /KLI-KLO. UA0 has a Pulldown. The
value is approximately 75 kOhm. For further
details refer to the application notes at the end of
this datasheet.
Applications:
The PE12016G/12024G enables mechanical
devices to be interlaced with micro-processors. It
may be used in many diverse applications,
including robotics, printers/plotters, tracker balls
(or mouse), lathes and machine tools,
automobiles, conveyor belts and transport
mechanisms.
Architecture:
The four main elements of the PE12016G are
shown in Fig 2:
1. The measurement and mode control logic
generates up or down count pulses,
internal signals (I1 and I2) from the
quadrature signals Ua1 and Ua2, the
clock input and from Mode Controls (M0,
M1, M2).
2. The control logic provides common
microprocessor interface signals.
3. The output multiplexer allows the
processor to select data from either the
upper (MS-byte) or the lower (LS-byte)
4. The 3-state buffers place this data on the
bus
The PE12024G-architecture, shown in Figure: 3,
is very similar to that of the PE12016G, except
for the up/down counter which has 24-bits and
can be independently reset by Ua0. The
cascading feature has also been removed.
December 15, 2005 (Version 1.7)
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PE12016G/24G
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