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PDF W83627UHG Data sheet ( Hoja de datos )

Número de pieza W83627UHG
Descripción WINBOND LPC I/O
Fabricantes Winbond　
Logotipo Winbond Logotipo



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No Preview Available ! W83627UHG Hoja de datos, Descripción, Manual

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W83627UHG
WINBOND LPC I/O
Date: May/25/2007 Revision: 1.0

1 page




W83627UHG pdf
W83627UHG
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Configuration Register - Index 40h (Bank 0) ................................................................ 65
Interrupt Status Register 1 - Index 41h (Bank 0) .......................................................... 66
Interrupt Status Register 2 - Index 42h (Bank 0) .......................................................... 66
SMI# Mask Register 1 - Index 43h (Bank 0)................................................................. 67
SMI# Mask Register 2 - Index 44h (Bank 0)................................................................. 67
Reserved Register - Index 45h (Bank 0) .................................................................... 68
SMI# Mask Register 3 - Index 46h (Bank 0)................................................................. 68
Fan Divisor Register I - Index 47h (Bank 0) ................................................................. 68
Serial Bus Address Register - Index 48h (Bank 0) ....................................................... 68
CPUFANOUT monitor Temperature source select register - Index 49h (Bank 0) ....... 69
SYSFANOUT monitor Temperature source select register - Index 4Ah (Bank 0) ....... 70
Fan Divisor Register II - Index 4Bh (Bank 0) ................................................................ 70
SMI#/OVT# Control Register - Index 4Ch (Bank 0)...................................................... 71
FAN IN/OUT Control Register - Index 4Dh (Bank 0) .................................................... 72
Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) .................................. 72
Winbond Vendor ID Register - Index 4Fh (Bank 0) ...................................................... 73
Reserved Register - Index 50h ~ 55h (Bank 0) ............................................................ 73
BEEP Control Register 1 - Index 56h (Bank 0) ............................................................ 73
BEEP Control Register 2 - Index 57h (Bank 0) ............................................................ 74
Chip ID - Index 58h (Bank 0) ........................................................................................ 75
Diode Selection Register - Index 59h (Bank 0) ............................................................ 75
Reserved Register - Index 5Ah ~ 5Ch (Bank 0) ........................................................... 75
VBAT Monitor Control Register - Index 5Dh (Bank 0) .................................................. 75
Critical Temperature enable register - Index 5Eh (Bank 0) .......................................... 76
Reserved Register - Index 5Fh (Bank 0) ...................................................................... 77
Reserved Registers - Index 60h (Bank 0) .................................................................... 77
Reserved Registers - Index 61h (Bank 0) .................................................................... 77
Reserved Registers - Index 62h (Bank 0) .................................................................... 77
Reserved Registers - Index 63h (Bank 0) .................................................................... 77
Reserved Registers - Index 64h (Bank 0) .................................................................... 77
Reserved Registers - Index 65h (Bank 0) .................................................................... 77
Reserved Registers - Index 66h (Bank 0) .................................................................... 77
CPUFANOUT Maximum Output Value Register - Index 67h (Bank 0) ........................ 77
CPUFANOUT Output Step Value Register - Index 68h (Bank 0)................................. 78
Reserved Registers - Index 69h (Bank 0) .................................................................... 78
Reserved Registers - Index 6Ah (Bank 0) .................................................................... 78
SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0)............................... 78
CPUFANOUT Critical Temperature register - Index 6Ch (Bank 0) .............................. 78
Reserved Registers - Index 6Dh (Bank 0).................................................................... 79
Reserved Registers - Index 6Eh (Bank 0) .................................................................... 79
CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 1) ...................... 79
CPUTIN/PECI Temperature (Low Byte) Register - Index 51h (Bank 1)....................... 79
CPUTIN Configuration Register - Index 52h (Bank 1).................................................. 80
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W83627UHG arduino
W83627UHG
List of Tables-
Table 6-1 Devices of I/O Base Address .......................................................................................... 22
Table 6-2 Chip (Global) Control Registers ...................................................................................... 25
Table 7-1 Temperature Data Format .............................................................................................. 33
Table 7-2 SST Command Summary ............................................................................................... 36
Table 7-3 Typical Temperature Values ........................................................................................... 37
Table 7-4 Fan Divisor Definition...................................................................................................... 40
Table 7-5 Divisor, RPM, and Count Relation .................................................................................. 40
Table 7-6 Display Registers – at SMART FANTM I Mode................................................................ 44
Table 7-7 Relative Registers – at Thermal Cruise Mode ................................................................ 45
Table 7-8 Relative Registers – at Speed Cruise Mode................................................................... 45
Table 7-9 Display Register – at SMART FANTMIII Mode ................................................................ 48
Table 7-10 Relative Register – at SMART FANTMIII Control Mode................................................. 49
Table 9-1 The Delays of the FIFO................................................................................................... 88
Table 9-2 FDC Registers................................................................................................................. 98
Table 10-1 Register Summary for UART ...................................................................................... 112
Table 11-1 Pin Descriptions for SPP, EPP, and ECP Modes ....................................................... 118
Table 11-2 EPP Register Addresses ............................................................................................ 118
Table 11-3 Address and Bit Map for SPP and EPP Modes .......................................................... 119
Table 11-4 ECP Mode Description................................................................................................ 123
Table 11-5 ECP Register Addresses ............................................................................................ 124
Table 11-6 Bit Map of the ECP Registers ..................................................................................... 124
Table 12-1 Bit Map of Status Register .......................................................................................... 133
Table 12-2 KBC Command Sets................................................................................................... 134
Table 13-1 Bit Map of Logical Device A, CR[E4h], Bits [6:5] ........................................................ 140
Table 13-2 Definitions of Mouse Wake-Up Events ....................................................................... 142
Table 13-3 Timing and Voltage Parameters of RSMRST# ........................................................... 143
Table 14-1 SERIRQ Sampling Periods ......................................................................................... 146
Table 16-1 Relative Control Registers of GPIO 25, 26 and 27 that Support Wake-Up Function . 149
Table 16-2 GPIO Register Addresses........................................................................................... 150
-X-

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