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PDF ML12210 Data sheet ( Hoja de datos )

Número de pieza ML12210
Descripción Serial Input PLL Frequency Synthesizer
Fabricantes LANSDALE Semiconductor 
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ML12210
Serial Input PLL
Frequency Synthesizer
Legacy Device: Motorola MC12210
The ML12210 is a 2.5 GHz Bipolar monolithic serial input
phase locked loop (PLL) synthesizer with pulse–swallow function.
It is designed to provide the high frequency local oscillator signal
of an RF transceiver in handheld communication applications.
The technology used allows for low power operation at a mini-
mum supply voltage of 2.7 V. The device is designed for operation
over 2.7 to 5.5 V supply range for input frequencies up to 2.5 GHz
with a typical current drain of 9.5 mA. The low power consump-
tion makes the ML12210 ideal for handheld battery operated
applications such as cellular or cordless telephones, wireless LAN
or personal communication services. A dual modulus prescaler is
integrated to provide either a 32/33 or 64/65 divide ratio.
• Low Power Supply Current of 8.8 mA Typical for ICC
and 0.7 mA Typical for Ip
• Supply Voltage of 2.7 to 5.5 V
• Dual Modulus Prescaler With Selectable Divide Ratios
of 32/33 or 64/65
• On–Chip Reference Oscillator/Buffer
• Programmable Reference Divider Consisting of a
Binary 14–Bit Programmable Reference Counter
• Programmable Divider Consisting of a Binary 7–Bit
Swallow Counter and an 11–Bit Programmable Counter
• Phase/Frequency Detector With Phase Conversion Function
• Balanced Charge Pump Outputs
• Dual Internal Charge Pumps for Bypassing the First
Stage of the Loop Filter to Decrease Lock Time
• Outputs for External Charge Pump
• Operating Temperature Range of TA = –40 to 85°C
NOTE: Also available is the ML12202, a 1.1 GHz version of this
function.
16
1
SO 16 = -5P
PLASTIC PACKAGE
CASE 751B
(SO–16)
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE MOTOROLA LANSDALE
SO 16
MC12210D ML12210-5P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
MAXIMUM RATINGS (Note 1)
Parameter
Power Supply Voltage, Pin 4
Symbol
VCC
Value
–0.5 to 6.0
Unit
Vdc
Power Supply Voltage, Pin 3
Vp VCC to 6.0 Vdc
Storage Temperature Range
Tstg
–65 to 150
°C
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation should be restricted to the Recommended
Operating Conditions.
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ML12210 pdf
ML12210
LANSDALE Semiconductor, Inc.
PROGRAMMABLE DIVIDER
19–bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18–bit shift
register into the 18–bit latch which specifies the swallow A–counter divide ratio (0 to 127) and the programmable N–counter divide ratio
(16 to 2047). An N–counter divide ratio less than 16 is prohibited.
For Control bit (C) = LOW:
MSB (FIRST BIT)
CONTROL BIT (LAST BIT)
LSB
NNNNNNNNNNNAAAAAAAC
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SETTING BITS FOR
DIVIDE RATIO OF
PROGRAMMABLE N–COUNTER
SETTING BITS FOR
DIVIDE RATIO OF
SWALLOW A–COUNTER
DIVIDE RATIO OF PROGRAMMABLE N–COUNTER
DIVIDE RATIO OF SWALLOW A–COUNTER
Divide N N N N N N N N N N N Divide A A A A A A A
Ratio N 18 17 16 15 14 13 12 11 10 9 8 Ratio A 7 6 5 4 3 2 1
16 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1
• ••••••••••• • •••••••
2047 1 1 1 1 1 1 1 1 1 1 1 127 1 1 1 1 1 1 1
DIVIDE RATIO SETTING
fvco = [(P • N)+A] • fosc ÷ R with A<N
fvco: Output frequency of external voltage controlled oscillator (VCO)
N: Preset divide ratio of binary 11–bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7–bit swallow counter (0 to 127, A<N)
fosc: Output frequency of the external frequency oscillator
R: Preset divide ratio of binary 14–bit programmable reference counter (8 to 16383)
P: Preset mode of dual modulus prescaler (32 or 64)
Figure 2. Serial Data Input Timing
DATA
N18:MSB
(SW:MSB)
N17
(R14)
N8 A7
(R7) (R6)
A1 C = CONTROL BIT (LAST BIT)
(R1) (C = CONTROL BIT (LAST BIT))
CLK
LE
Page 5 of 11
ts(CLE)
ts(D) th(D) tCW
NOTES: Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK.
ts(D) = Setup Time DATA to CLK
th(D) = Hold Time DATA to CLK
tCW = CLK Pulse Width
tEW = LE Pulse Width
ts(CLE) = Setup Time CLK to LE
ts(D) 10 ns
th(D) 20 ns
tCW 30 ns
tEW 20 ns
ts(CLE) 30 ns
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tEW
Issue A

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ML12210 arduino
ML12210
LANSDALE Semiconductor, Inc.
–A
16
1
OUTLINE DIMENSIONS
9
–B
8
SO 16 = -5P
PLASTIC PACKAGE
(ML12210-5P)
CASE 751B–05
(SO–16)
ISSUE J
P 8 PL
0.25 (0.010) M B M
–T
SEATING
PLANE
G
K
C
D 16 PL
0.25 (0.010) M T B S A S
M
R X 45°
F
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOW ABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 11 of 11
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