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PDF YSS922 Data sheet ( Hoja de datos )
| Número de pieza | YSS922 | |
| Descripción | 96kHz DIR + Dolby Digital / Pro Logic / DTS decoder + Sub DSP | |
| Fabricantes | YAMAHA | |
| Logotipo |  |
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YSS922
Preliminary
AC3D3
96kHz DIR + Dolby Digital / Pro Logic / DTS decoder + Sub DSP
OUTLINE
YSS922 is one chip LSI consisting of three built-in blocks : Dolby Digital (AC-3) / Pro Logic & DTS decoder
(Main DSP), a programmable sound processing DSP (Sub DSP) and SPDIF receiver (DIR) which can handle up to
96kHz sampling frequency. The Sub DSP is capable of realizing various sound fields, such as virtual surround by
down-loading the program and coefficient from outside.
FEATURES
DIR Block
· Sampling frequency: two ranges are available including;
32k to 48kHz (normal rate) and
64k to 96kHz (double rate)
· Provides master clock, 256fs, to DAC, ADC and other peripheral devices. The clock output can be controlled
with various modes determined by register setting.
· Has a pin that indicates the double rate operation.
· Every channel status and user data can be read through the microprocessor interface.
· Has an output pin for interrupt that is activated by changing of the status information.
· Internal operation frequency: 25MHz
Main DSP Block
· Dolby Digital (AC-3) / Pro Logic and DTS decode
· High quality internal 24 bit DSP
· No external memory is required. (Memory for center and surround channel delay is included.)
· AC-3 Karaoke mode.
· Supports compression modes at AC-3 / DTS decoding.
· Pro Logic decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM signal.
· Reads Dolby Digital / DTS decode information through the microprocessor interface.
· Included de-emphasis filter for the PCM signal.
· Internal operation frequency: 30MHz
YAMAHA CORPORATION
www.DataSheet4U.com
YSS922 CATALOG
CATALOG No.: LSI-4SS922A1
2000.2
1 page  
YSS922
PIN FUNCTION
No. Name
1 TESTXI
2 TESTXO
3 VDD2
4 XO
5 XI
6 TESTMS
7 TESTXEN
8 IPORT0
9 IPORT1
10 IPORT2
11 IPORT3
12 IPORT4
13 DDIN0
14 DDIN1
15 DDIN2
16 DDIN3
17 VSS
18 CPO
19 AVDD
20 DIRPCO
21 DIRPRO
22 AVSS
23 TESTBRK
24 TESTR1
25 TESTR2
26 VDD1
27 SDWCKI0
28 SDBCKI0
29 /SDBCKO
30 SDIA
31 SDOA2
32 SDOA1
33 SDOA0
34 SDIB3
35 SDIB2
36 SDIB1
37 SDIB0
38 VSS
39 VDD2
40 DIRSDO
41 DIRWCK
42 DIRBCK
43 DIRMCK
44 ERR/BS
45 SYNC/U
46 FS128/C
47 DBL/V
48 SDWCKI1
49 SDBCKI1
50 VSS
51 SDOB3
52 SDOB2
53 SDOB1
54 SDOB0
55 VDD1
I/O
I
O
-
O
I
I+
I+
I+
I+
I+
I+
I+
Is
Is
Is
Is
-
A
-
A
A
-
I+
I+
I+
-
I+
I+
O
I
O
O
O
I+
I+
I+
I+
-
-
O
O
O
O
O
O
O
O
I+
I+
-
O
O
O
O
-
Function
LSI Test Pin (must be connected to VSS)
LSI Test Pin (to be open)
+2.5V Power Supply (for Internal Core Logic)
Crystal oscillator connection
Crystal oscillator connection (24.576MHz)
LSI Test Pin (to be open)
LSI Test Pin (to be open)
General purpose input port
General purpose input port
General purpose input port
General purpose input port
General purpose input port
DIR: Digital audio interface data input 0
DIR: Digital audio interface data input 1 / General purpose input port
DIR: Digital audio interface data input 2 / General purpose input port
DIR: Digital audio interface data input 3 / General purpose input port
Ground
PLL filter connection
+3.3V Power Supply (for DIR block)
DIR: PLL filter connection
DIR: PLL filter connection
Ground (for DIR block)
LSI Test Pin (to be open)
LSI Test Pin (to be open)
LSI Test Pin (to be open)
+3.3V Power Supply (for I/O)
Word clock input for SDIA, SDOA, SDIB, SDOB
Bit clock input for SDIA, SDOA, SDIB, SDOB
Reverse clock output of DIRBCK or SDBCKI0
Input of bitstream or PCM data to Main DSP
PCM data output from Main DSP (C, LFE)
PCM data output from Main DSP (LS, RS)
PCM data output from Main DSP (L, R)
PCM data input to Sub DSP
PCM data input to Sub DSP
PCM data input to Sub DSP
PCM data input to Sub DSP
Ground
+2.5V Power Supply (for Internal Core Logic)
Output of bitstream or PCM data from DIR
DIR: Serial data word clock (fs) output
DIR: Serial data bit clock (64fs) output
DIR: Serial data master clock (256fs or 128fs) output
DIR: Data error detect / block start output
DIR: Serial data synchronized timing / User data output
DIR: Serial data master clock 128fs / Channel status output
DIR: Double rate lock detect / Validity flag output
Word clock input for SDIB, SDOB
Bit clock input for SDIB, SDOB
Ground
PCM data output from Sub DSP
PCM data output from Sub DSP
PCM data output from Sub DSP
PCM data output from Sub DSP
+3.3V Power Supply (for I/O)
5
5 Page 
YSS922
1-2-2. Status output
· DTSDATA, AC3DATA, SURENC, KARAOKE, MUTE, CRC, NONPCM
These pins output the status data of the signals processed in the Main DSP block.
The status, which is the same as the contents of the Status Register, is output from respective pins.
· ZEROFLG
This pin indicates how long the input signal (SDIA or DIRSDO) for the Main DSP block is kept in the digital
zero state. The same status as ZEROFLG of the ZERO Register is output.
1-3. Sub DSP Block
1-3-1. Serial data input / output
· SDIB0-3
These are PCM input pins to the Sub DSP block.
The data input to SDIB0-2 pins or the SDOA0-2 output from the Main DSP block are selected by SDIBSEL
and processed in the Sub DSP block. The input data to the SDIB3 pin is always processed in the Sub DSP
block regardless of SDIBSEL.
The input format can be selected by setting the SDIB register.
· SDOB0-3
This is the output pin for the PCM signals processed in the Sub DSP block.
The output format can be selected by setting the SDOB register.
1-3-2. External memory interface
· RAMA0-17, RAMD0-15, RAMWEN, RAMOEN, CASN, RASN
These pins are used to connect an external memory to the Sub DSP block for the data delay.
1-3-3. Status output
· OVFB / END
The output varies depending on OVFSEL settings of ERAM register, bit7.
This output is used when programming Sub DSP.
OVFB at OVFSEL=0
This pin becomes “H” level when a digital overflow occurs as a result of operation in the Sub DSP block.
“H” level is kept from the moment an overflow occurs to the moment the next PCM sample is output from
the SDOB interface. When the next PCM sample output starts, the pin is reset to “L” level.
END at OVFSEL=1
This pin becomes “H” level while the program counter of Sub DSP is operating, and “L” level when all the
processing is completed and the program counter stops. While operating correctly, it becomes “L” level
once during one sample time. If it fails to become “L” level even once during one sample time, it means
that the program has not been completed correctly and fully.
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet YSS922.PDF ] | |
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