D72042 반도체 회로 부품 판매점
UPD72042
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 NEC |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72042
LSI DEVICES FOR Inter Equipment BusTM (IEBusTM)
PROTOCOL CONTROL
The µPD72042 is a microcomputer peripheral LSI device for IEBus protocol control.
The µPD72042 performs all the processing required for layers 1 and 2 of the IEBus. The devices incorporate large
transmission and reception buffers, allowing the microcomputer to perform IEBus operations without interruption.
They also contain an IEBus driver and receiver, allowing them to directly connected to the bus directly.
FEATURES
• Control of layers 1 and 2 of the IEBus protocol
• Support of a multi-master scheme
• Broadcast function
• Two communication modes having different
transmission speeds can be selected.
Mode 0
Mode 1
Transmission speed
Approx. 3.9 Kbps
Approx. 17 Kbps
q Built-in IEBus driver and receiver
q Transmission and reception buffers
Transmission buffer : 33 bytes, FIFO
Reception buffer
: 40 bytes, FIFO (capable of
holding more than one frame
of reception data.)
ORDERING INFORMATION
• Microcomputer interface
Three-/two-wire serial I/O,
Transfer starting with MSB
• Program crashes can be detected by means of a
watchdog timer.
• Low power consumption (standby mode):
50 µA (max)
• Oscillator frequency (fX): 6 MHz
• frequency accuracy: ±1.5%
• Operating voltage: 5 V ±10%
Part number
µPD72042GT
Package
16-pin plastic SOP (9.53 mm (375))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14870EJ1V0DS00 (1st edition)
Date Published June 2000 N CP(N)
Printed in Japan
www.DataSheet.in
©
2000
PIN CONFIGURATION (TOP VIEW)
• 16-pin plastic SOP (9.53 mm (375))
µPD72042GT
SCK
SI(SIO)Note
SO(NC)Note
IRQ
C/D
XI
XO
GND
1
2
3
4
5
6
7
8
16 VDD
15 TEST
14 RESET
13 CS
12 SEL
11 AVDD
10 BUS+
9 BUS−
Note Parentheses indicate the state corresponding to two-wire serial I/O mode.
AVDD
: Main power supply for IEBus (connected to the VDD pin)
BUS–, BUS+ : IEBus I/O
C/D : Command/data switch input
CS : Chip select input
GND
: Ground
IRQ : Interrupt request output
NC : No connection
RESET
: Reset input
SCK
: Serial clock input
SEL : Serial mode selection
SI : Serial data input
SIO : Serial data I/O
SO : Serial data output
TEST
: Test input (connected to the VDD pin)
VDD : Main power supply
XI, XO
: System clock
µPD72042
2
www.DataSheet.in
Data Sheet S14870EJ1V0DS00
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D72042 data
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